Icestorm: LD1R (4S) measurements

Code:

  ld1r { v0.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29703	2018	1	1015	1002	1002	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29390	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29374	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29367	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29589	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29367	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29386	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29404	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29574	2003	1	1002	1000	1000	1000	3000	7775	2000	1000	1000	1000	1000	1	1000	1000
62004	30351	2003	1	1002	1000	1000	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120154	70114	40101	20012	10001	30130	20031	10004	3208937	1257536	2575597	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60294	10016	20032	40007	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60294	10016	20033	40006	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120053	70105	40101	20004	10000	30103	20007	10004	3209017	1257705	2575897	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20007	10004	3209098	1257741	2575966	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120145	70024	40011	20012	10001	30040	20031	10000	3208987	1259154	2578452	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120050	70015	40011	20004	10000	30010	20000	10016	3209493	1259456	2579046	60090	30071	10016	20033	60264	10154	20033	40070	10034	10000	40100
60025	120094	70024	40016	20007	10001	30040	20023	10000	3208979	1259224	2578563	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60122	10016	20033	40006	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3208871	1259176	2578471	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]
  ld1r { v0.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40293	160269	101	80129	80039	100	80039	80054	300	240502	641548	160208	200	80054	80054	200	80012	80012	1	80000	80000	100
160204	40105	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40496	160139	101	80030	80008	100	80012	80012	300	257831	662503	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40106	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40108	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40106	160139	101	80030	80008	100	80012	80012	300	244382	646288	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40569	160379	101	80150	80128	100	80180	80012	300	264972	672433	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40504	160179	11	80129	80039	10	80039	80012	30	240278	640660	160034	20	80012	80012	20	80012	80012	1	80000	80000	10
160024	40079	160047	11	80036	80000	10	80000	80055	30	240515	641052	160120	20	80055	80055	20	80000	80000	1	80000	80000	10
160024	40068	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40064	160047	11	80036	80000	10	80000	80000	30	240242	640580	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations