Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1R (8B)

Test 1: uops

Code:

  ld1r { v0.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.001

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
620053000320361102910060100610003000777020001000100010001000110001000
620042943420031100210000100010003000776220001000100010001000110001000
620042941720021100110000100010003000776220001000100010001000110001000
620042941920021100110000100010003000776220001000100010001000110001000
620042940220021100110000100010003000776220001000100010001000110001000
620042941620021100110000100010003000776220001000100010001000110001000
620042941920021100110000100010003000776220001000100010001000110001000
620042951620021100110000100010003000776220001000100010001000110001000
620042957620021100110000100010003000776220001000100010001000110001000
620042952220021100110000100010003000776220001000100010001000110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60205120154701144010120012100013013020030100043208929126913225874236011430212100042000860222100042000840001100001000040100
60204120053701054010120004100003010320006100043209037130618026254606011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100
60205120086701154010520008100023013320030100043209334130631226257066011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100
60205120082701144010620007100013013320030100043209010130616826254386011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100
60204120049701054010120004100003010320006100043209010130616826254386011330211100042000860222100042000840001100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60025120158700244001120012100013004020031100043209188125936125788456002430032100042000860020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100163209472125945325790366009030071100162003360020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209114125927525786786001030020100002000060020100002000040001100001000040010
60024120052700154001120004100003001020000100113209613130654026262256007430057100122002560020100002000040001100001000040010
60024120050700154001120004100003001020000100003209087125926425786566001030020100002000060020100002000040001100001000040010
60024120049700154001120004100003001020000100003209168125929925787256001030020100002000060020100002000040001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5014

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020540250160267101801288003810080038800123002402786406601601242008001280012200800128001218000080000100
16020440111160153101800448000810080012800123002591806652871601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440111160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100
16020440109160151101800428000810080012800123002402786406601601242008001280012200800128001218000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002540748160177118012880038108003880000302402326410521600102080000800002080000800001800008000010
16002440089160049118003880000108000080000303065307307951600102080000800002080000800001800008000010
16002440054160035118002480000108000080000302401346404241600102080000800002080000800001800008000010
16002440105160035118002480000108000080000302401346404241600102080000800002080000800001800008000010
16002440054160035118002480000108000080000302401346404241600102080000800002080000800001800008000010
16002440054160035118002480000108000080000302401346404241600102080000800002080000800001800008000010
16002440054160035118002480000108000080000302401346404241600102080000800002080000800001800008000010
16002440107160035118002480000108000080000303132427371011600102080000800002080012800121800008000010
16002440067160031118002080000108000080000302401686403401600102080000800002080000800001800008000010
16002440056160031118002080000108000080000302401686403401600102080000800002080000800001800008000010