Icestorm: LD1R (8B) measurements

Code:

  ld1r { v0.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.001

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	30003	2036	1	1029	1006	0	1006	1000	3000	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	29434	2003	1	1002	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29417	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29419	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29402	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29416	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29419	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29516	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29576	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000
62004	29522	2002	1	1001	1000	0	1000	1000	3000	7762	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120154	70114	40101	20012	10001	30130	20030	10004	3208929	1269132	2587423	60114	30212	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120053	70105	40101	20004	10000	30103	20006	10004	3209037	1306180	2625460	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60205	120086	70115	40105	20008	10002	30133	20030	10004	3209334	1306312	2625706	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60205	120082	70114	40106	20007	10001	30133	20030	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100
60204	120049	70105	40101	20004	10000	30103	20006	10004	3209010	1306168	2625438	60113	30211	10004	20008	60222	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120158	70024	40011	20012	10001	30040	20031	10004	3209188	1259361	2578845	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10016	3209472	1259453	2579036	60090	30071	10016	20033	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209114	1259275	2578678	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120052	70015	40011	20004	10000	30010	20000	10011	3209613	1306540	2626225	60074	30057	10012	20025	60020	10000	20000	40001	10000	10000	40010
60024	120050	70015	40011	20004	10000	30010	20000	10000	3209087	1259264	2578656	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120049	70015	40011	20004	10000	30010	20000	10000	3209168	1259299	2578725	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]
  ld1r { v0.8b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5014

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40250	160267	101	80128	80038	100	80038	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160153	101	80044	80008	100	80012	80012	300	259180	665287	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40111	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40109	160151	101	80042	80008	100	80012	80012	300	240278	640660	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40748	160177	11	80128	80038	10	80038	80000	30	240232	641052	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40089	160049	11	80038	80000	10	80000	80000	30	306530	730795	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40054	160035	11	80024	80000	10	80000	80000	30	240134	640424	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40105	160035	11	80024	80000	10	80000	80000	30	240134	640424	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40054	160035	11	80024	80000	10	80000	80000	30	240134	640424	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40054	160035	11	80024	80000	10	80000	80000	30	240134	640424	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40054	160035	11	80024	80000	10	80000	80000	30	240134	640424	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40107	160035	11	80024	80000	10	80000	80000	30	313242	737101	160010	20	80000	80000	20	80012	80012	1	80000	80000	10
160024	40067	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40056	160031	11	80020	80000	10	80000	80000	30	240168	640340	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (8B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations