Icestorm: LD1R (8H) measurements

Code:

  ld1r { v0.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.001

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch simd uop (57)	dispatch ldst uop (58)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	30600	2036	1	1029	1006	1006	1000	3000	7767	2000	1000	1000	1000	1000	1	1000	1000
62004	29679	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	30422	2003	1	1002	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29446	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29516	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29721	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29661	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29544	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000
62004	29527	2002	1	1001	1000	1000	1000	3010	7770	2000	1000	1000	1000	1000	1	1000	1000
62004	30342	2002	1	1001	1000	1000	1000	3000	7760	2000	1000	1000	1000	1000	1	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120147	70114	40101	20012	10001	30130	20031	10004	3208883	1257514	2575551	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120073	70112	40106	20005	10001	30133	20029	10004	3208728	1257518	2575533	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120050	70105	40101	20004	10000	30103	20007	10004	3209079	1257661	2575832	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120042	70103	40101	20002	10000	30103	20007	10004	3208828	1257628	2575736	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60205	120103	70112	40106	20005	10001	30133	20030	10004	3208836	1257562	2575625	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208828	1257630	2575736	60114	30212	10004	20008	60302	10016	20033	40006	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20006	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100
60204	120040	70103	40101	20002	10000	30103	20007	10004	3208774	1257606	2575690	60114	30212	10004	20008	60224	10004	20008	40001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120157	70024	40011	20012	10001	30040	20031	10004	3209019	1259221	2578586	60024	30032	10004	20008	60020	10000	20000	40001	10000	10000	40010
60024	120047	70015	40011	20004	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60025	120073	70022	40016	20005	10001	30043	20029	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60118	10016	20033	40006	10000	10000	40010
60024	120050	70013	40011	20002	10000	30010	20000	10000	3208844	1259165	2578449	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010
60024	120040	70013	40011	20002	10000	30010	20000	10000	3208871	1259176	2578471	60010	30020	10000	20000	60020	10000	20000	40001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]
  ld1r { v0.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5013

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	40344	160267	101	80128	80038	100	80038	80012	300	240268	641164	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40113	160153	101	80044	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80054	80054	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40106	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40103	160139	101	80030	80008	100	80012	80012	300	240142	641662	160124	200	80012	80012	200	80012	80012	1	80000	80000	100
160204	40105	160139	101	80030	80008	100	80012	80012	300	240170	640504	160124	200	80012	80012	200	80012	80012	1	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5008

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	40485	160179	11	80129	80039	10	80039	80000	30	240232	641068	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40077	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80054	30	240502	653076	160118	20	80054	80054	20	80000	80000	1	80000	80000	10
160024	40136	160049	11	80038	80000	10	80000	80000	30	314754	743487	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40075	160049	11	80038	80000	10	80000	80000	30	300754	737122	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	647020	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10
160024	40062	160049	11	80038	80000	10	80000	80000	30	240232	652612	160010	20	80000	80000	20	80000	80000	1	80000	80000	10

LD1R (8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations