Icestorm: LD1R (post-index, 16B) measurements

Code:

  ld1r { v0.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29750	3042	1007	1029	1006	1006	1006	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29343	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29387	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29343	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29379	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29387	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29345	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29379	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29383	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29343	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.16b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120147	80115	50102	20012	10001	40132	20024	10003	3199227	943511	1952166	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60205	120080	80115	50107	20007	10001	40135	20025	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60205	120080	80115	50107	20007	10001	40135	20025	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3199121	943564	1952238	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120040	80103	50101	20002	10000	40104	20006	10003	3201119	944223	1953530	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120155	80025	50012	20012	10001	40042	20024	10003	3199412	944590	1954273	70023	30029	10004	20007	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120103	80015	50011	20004	10000	40014	20006	10012	3200572	944992	1955067	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10012	3199867	947480	1936034	70082	30059	10014	20026	60020	20000	20000	50001	10000	10000	40010
60024	120053	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199432	944607	1954296	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8
  ld1r { v0.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80148	240283	80131	80122	80030	80136	80032	80008	1399671	1359461	1799520	240126	200	80009	80009	200	160014	80007	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80107	80007	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160076	80038	80031	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160072	80036	80031	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80208	240283	80071	80152	80060	80076	80062	80006	1399494	1359547	1799716	240028	20	80006	80006	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160025	80103	240139	80041	80068	80030	80049	80039	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399596	1359615	1799675	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10

LD1R (post-index, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations