Icestorm: LD1R (post-index, 2D) measurements

Code:

  ld1r { v0.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29884	3041	1007	1028	1006	1006	1006	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29287	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29288	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29290	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29333	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29307	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29303	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29301	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29291	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29288	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120155	80115	50102	20012	10001	40132	20024	10003	3199093	943571	1951431	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60205	120075	80113	50107	20005	10001	40135	20024	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60278	20028	20027	50007	10000	10000	40100
60204	120061	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120147	80025	50012	20012	10001	40042	20024	10003	3199358	944574	1954237	70023	30029	10004	20007	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10012	3199812	944740	1954570	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120049	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60025	120080	80025	50017	20007	10001	40045	20025	10000	3199918	944771	1954610	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120047	80015	50011	20004	10000	40010	20000	10000	3199378	944591	1954260	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8
  ld1r { v0.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80139	240283	80131	80122	80030	80136	80032	80007	1399528	1359345	1799474	240121	200	80007	80007	200	160074	80037	80031	80000	80000	100
160204	80040	240125	80101	80024	80000	80107	80007	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160205	80102	240214	80132	80053	80029	80137	80035	80007	1399806	1359604	1799770	240123	200	80008	80008	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160072	80036	80031	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	80139	240193	80041	80122	80030	80049	80035	80007	1399412	1359438	1800245	240031	20	80007	80007	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80006	1399555	1359602	1799796	240028	20	80006	80006	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80016	80006	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160072	80036	80031	80000	80000	10

LD1R (post-index, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations