Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1R (post-index, 2S)

Test 1: uops

Code:

  ld1r { v0.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200529508301910031014100210021002100030003000777030001000100020001000100110001000
6200429333300310011002100010001000100030003000777030001000100020001000100110001000
6200429301300310011002100010001000100030003000777030001000100020001000100110001000
6200429297300310011002100010001000100030003000777030001000100020001000100110001000
6200429295300310011002100010001000100030003000777030001000100020001000100110001000
6200429305300310011002100010001000100030003000777030001000100020001000100110001000
6200429390300310011002100010001000100030003001777330001000100020001000100110001000
6200429773300310011002100010001000100030003000777030001000100020001000100110001000
6200429305300310011002100010001000100030003000777030001000100020001000100110001000
6200429328300310011002100010001000100030003000777030001000100020001000100110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020512015580115501022001210001401322002410003319917694345119520567011330209100042000760218200082000750001100001000040100
6020512007380113501072000510001401352002510003319902994345919520497011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319885194348419520587011330209100042000760278200282002750007100001000040100
6020412012680107501012000610000401042000610003319903994342019519857011330209100042000760218200082000750001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200082000750001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200082000750001100001000040100
6020412004280103501012000210000401042000610003319917594358019522747011330209100042000760218200082000750001100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002512015380025500122001210001400422002410003319945494464519543737002330029100042000760038200082000750001100001000040010
6002412004280013500112000210000400102000010000319924394455119541707001030020100002000060020200002000050001100001000040010
6002412004280013500112000210000400102000010000319924394455119541707001030020100002000060020200002000050001100001000040010
6002412004980015500112000410000400102000010000319924394455119541707001030020100002000060020200002000050001100001000040010
6002512008280025500172000710001400452002310000319924394455119541707001030020100002000060020200002000050001100001000040010
6002412004280013500112000210000400102000010000319924394455119541707001030020100002000060020200002000050001100001000040010
6002412004280013500112000210000400102000010000319943294460719542967001030020100002000060020200002000050001100001000040010
6002412004280013500112000210000400102000010000319943294460719542967001030020100002000060020200002000050001100001000040010
6002412004280013500112000210000400102000010000319924394455119541707001030020100002000060020200002000050001100001000040010
6002512007580023500172000510001400452002510000319924394455119541707001030020100002000060020200002000050001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  ld1r { v0.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020680208240379801618015880060801668006280007139965513594661799606240121200800078000720016001480007800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020580097240207801318004680030801388003880006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002580148240193800418012280030800468003280000139937413594301799599240010208000080000201600728003680031800008000010
16002480036240021800118001080000800108000080000139963613596431799685240010208000080000201600008000080001800008000010
16002480036240021800118001080000800108000080000139963613596431799685240010208000080000201600008000080001800008000010
16002480036240021800118001080000800108000080000139963613596431799685240010208000080000201600008000080001800008000010
16002480036240021800118001080000800108000080000139914513592821799700240010208000080000201600008000080001800008000010
16002480040240035800118002480000800108000080000139952513595741799754240010208000080000201600008000080001800008000010
16002480040240035800118002480000800108000080000139952513595741799754240010208000080000201600008000080001800008000010
16002480040240035800118002480000800108000080000139952513595741799754240010208000080000201600008000080001800008000010
16002480040240035800118002480000800108000080000139952513595741799754240010208000080000201600008000080001800008000010
16002480040240035800118002480000800108000080000139952513595741799754240010208000080000201600008000080001800008000010