Icestorm: LD1R (post-index, 4H) measurements

Code:

  ld1r { v0.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29684	3019	1003	1014	1002	1002	1002	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29414	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29345	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29376	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29381	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29374	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29377	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29335	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29336	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000
62004	29338	3003	1001	1002	1000	1000	1000	1000	3000	3000	7767	3000	1000	1000	2000	1000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120153	80115	50102	20012	10001	40132	20024	10003	3199271	943525	1952199	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10012	3200100	943843	1952849	70172	30239	10014	20027	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120141	80105	50101	20004	10000	40104	20006	10003	3199634	943724	1952577	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10003	3199364	943636	1952400	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120049	80105	50101	20004	10000	40104	20006	10012	3200089	943832	1952808	70171	30239	10013	20026	60218	20008	20007	50001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60026	120322	80035	50018	20015	10002	40073	20043	10003	3199216	944531	1954142	70023	30029	10004	20007	60098	20028	20027	50007	10000	10000	40010
60024	120046	80013	50011	20002	10000	40010	20000	10000	3199243	944551	1954170	70010	30020	10000	20000	60080	20020	20020	50007	10000	10000	40010
60024	120047	80013	50011	20002	10000	40010	20000	10000	3199243	944551	1954170	70010	30020	10000	20000	60080	20020	20020	50007	10000	10000	40010
60024	120042	80013	50011	20002	10000	40010	20000	10000	3199243	944551	1954170	70010	30020	10000	20000	60098	20026	20026	50007	10000	10000	40010
60024	120042	80013	50011	20002	10000	40010	20000	10000	3199243	944551	1954170	70010	30020	10000	20000	60158	20044	20045	50013	10000	10000	40010
60024	120046	80013	50011	20002	10000	40010	20000	10012	3201324	945233	1955540	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010
60024	120042	80013	50011	20002	10000	40010	20000	10009	3200805	948665	1930338	70068	30050	10009	20019	60020	20000	20000	50001	10000	10000	40010
60024	120042	80013	50011	20002	10000	40010	20000	10012	3200896	945107	1955268	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010
60024	120042	80013	50011	20002	10000	40010	20000	10000	3199243	944551	1954170	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60025	120124	80023	50017	20005	10001	40045	20024	10012	3200136	944840	1954779	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8
  ld1r { v0.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80144	240283	80131	80122	80030	80136	80032	80007	1399729	1359507	1799527	240121	200	80007	80007	200	160018	80009	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100
160204	80036	240113	80101	80012	80000	80108	80008	80007	1399887	1359651	1799688	240123	200	80008	80008	200	160016	80008	80001	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160026	80343	240283	80071	80152	80060	80079	80065	80007	1399412	1359464	1799703	240031	20	80007	80007	20	160018	80009	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160025	80111	240141	80041	80070	80030	80040	80030	80000	1399486	1359544	1799801	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10

LD1R (post-index, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations