Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1R (post-index, 8B)

Test 1: uops

Code:

  ld1r { v0.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.001

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.001

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
6200529924301910031014100210021002100030003001777130001000100020001000100110001000
6200429516300210011001100010001000100030003000776230001000100020001000100110001000
6200429305300210011001100010001000100030003000776230001000100020001000100110001000
6200429347300210011001100010001000100030003000776230001000100020001000100110001000
6200429324300210011001100010001000100030003000776230001000100020001000100110001000
6200429309300210011001100010001000100030003000776230001000100020001000100110001000
6200429335300210011001100010001000100030003000776230001000100020001000100110001000
6200429305300210011001100010001000100030003000776230001000100020001000100110001000
6200429356300210011001100010001000100030003000776230001000100020001000100110001000
6200429290300210011001100010001000100030003000776230001000100020001000100110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020612018880127501082001710002401632004210003319902894355619513987011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760278200282002750007100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760218200082000750001100001000040100
6020412004080103501012000210000401042000610003319912194356419522387011330209100042000760278200282002750007100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002512014980025500122001210001400422002410000319932994453319541557001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060096200262002650007100001000040010
6002412006480015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319954094464519543687001030020100002000060020200002000050001100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060096200262002650007100001000040010
6002412004780015500112000410000400102000010000319937894459119542607001030020100002000060020200002000050001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  ld1r { v0.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020580137240282801318012180030801378003380008139959813593751799372240126200800098000920016001480007800018000080000100
16020480036240111801018001080000801068000680007139976613595351799537240121200800078000720016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680037139852613587201799663240213200800388003820016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100
16020480036240111801018001080000801068000680006139991213596711799682240118200800068000620016001280006800018000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002580146240193800418012280030800468003280007139941213594611799729240031208000780007201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600728003680031800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600728003680031800008000010
16002480036240023800118001280000800108000080000139959613596151799675240010208000080000201600008000080001800008000010