Icestorm: LD1R (post-index, 8H) measurements

Code:

  ld1r { v0.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.002

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map ldst uop (7d)	map simd uop (7e)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)
62005	29581	3020	1003	1015	1002	1002	1002	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29400	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29383	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29363	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29351	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29364	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29315	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29349	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29654	3003	1001	1002	1000	1000	1000	1000	3000	3000	7770	3000	1000	1000	2000	1000	1001	1000	1000
62004	29812	3003	1001	1002	1000	1000	1000	1000	3000	3001	7771	3000	1000	1000	2000	1000	1001	1000	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1r { v0.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60205	120155	80115	50102	20012	10001	40132	20023	10003	3199271	943525	1952199	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120517	80183	50151	20022	10010	40274	20101	10003	3199310	943624	1952363	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60338	20048	20047	50021	10000	10000	40100
60204	120829	80215	50171	20030	10014	40342	20139	10075	3216479	949947	1958490	70609	30449	10084	20166	60634	20144	20143	50072	10000	10000	40100
60205	120302	80149	50129	20015	10005	40205	20063	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100
60204	120042	80103	50101	20002	10000	40104	20006	10003	3199175	943580	1952274	70113	30209	10004	20007	60218	20008	20007	50001	10000	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	120308	80025	50012	20012	10001	40042	20024	10003	3199169	944518	1954111	70023	30029	10004	20007	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40014	20006	10012	3199623	944684	1954444	70082	30059	10014	20027	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60038	20008	20007	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10012	3199612	944668	1954414	70083	30061	10013	20026	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010
60024	120040	80013	50011	20002	10000	40010	20000	10000	3199189	944535	1954134	70010	30020	10000	20000	60020	20000	20000	50001	10000	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8
  ld1r { v0.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160205	80148	240283	80131	80122	80030	80136	80032	80006	1399527	1359342	1799474	240120	200	80007	80007	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160072	80036	80031	80000	80000	100
160204	80040	240125	80101	80024	80000	80106	80006	80006	1399804	1359602	1799751	240118	200	80006	80006	200	160012	80006	80001	80000	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
160025	80137	240192	80041	80121	80030	80047	80033	80000	1399374	1359430	1799599	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80000	1399525	1359574	1799754	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80040	240035	80011	80024	80000	80010	80000	80007	1399557	1359597	1799912	240031	20	80007	80007	20	160012	80006	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10
160024	80042	240037	80011	80026	80000	80010	80000	80000	1399525	1359572	1799806	240010	20	80000	80000	20	160000	80000	80001	80000	80000	10

LD1R (post-index, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations