Icestorm: LD1 (multiple, 1 reg, 16B) measurements

Code:

  ld1 { v0.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
61005	29889	1008	1	1007	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29107	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29071	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29076	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29078	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29076	1001	1	1000	1000	3008	1000	1000	0	1000	0	1	1000	0	0
61004	29199	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29492	1001	1	1000	1000	3003	1000	1000	0	1000	0	1	1000	0	0
61004	29074	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0
61004	29080	1001	1	1000	1000	3000	1000	1000	0	1000	0	1	1000	0	0

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.16b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100148	60108	40101	10006	10001	30130	10014	10004	2669248	1045576	1070755	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100050	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60294	10017	10016	40005	10000	40100
50204	100062	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50205	100090	60112	40107	10004	10001	30133	10015	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669293	1045651	1070825	50110	30212	10004	10004	60296	10016	10017	40007	10000	40100
50204	100063	60103	40101	10002	10000	30103	10003	10004	2669164	1045538	1070719	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100158	60018	40011	10006	10001	30040	10014	10004	2669312	1046913	1071959	50020	30032	10004	10004	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50025	100149	60022	40017	10004	10001	30043	10015	10000	2669417	1046968	1072005	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100049	60013	40011	10002	10000	30010	10000	10000	2669147	1046858	1071895	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10000	2669336	1046935	1071972	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100042	60012	40011	10001	10000	30010	10000	10016	2671530	1047901	1072922	50074	30070	10017	10017	60114	10017	10016	40005	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]
  ld1 { v0.16b }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40192	80131	101	80030	100	80008	300	280030	80108	200	80012	200	80012	1	80000	100
80204	40062	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100
80204	40047	80101	101	80000	100	80008	300	640028	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40275	80047	11	80036	10	80000	30	640164	80010	20	80000	20	80000	1	80000	10
80025	40099	80048	11	80037	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639990	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10

LD1 (multiple, 1 reg, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations