Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 1D)

Test 1: uops

Code:

  ld1 { v0.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005298391003110021000300010001000100011000
61004295141001110001000300010001000100011000
61004299341001110001000300010001000100011000
61004291311001110001000300010001000100011000
61004291371001110001000300010001000100011000
61005291461002110011000300010001000100011000
61004294751001110001000300010001000100011000
61004291371001110001000301210001000100011000
61004299601001110001000300110001000100011000
61004291281001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5020510015360108401011000610001301301001410004266912310454661070652501103021210004100046030210016100174000710000040100
5020410004760103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410004760103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410004760103401011000210000301031000310004266929310456541070828501103021210004100046022410004100044000110000040100
5020510015160112401051000510002301331001510004266932010456651070839501103021210004100046022410004100044000110000040100
5020410004860103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410004760103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410004760103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410010660103401011000210000301031000310004266921210456181070792501103021210004100046022410004100044000110000040100
5020410042560155401331001310009302321005410004266921210456181070792501103021210004100046029410016100164000910000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001556001840011100061000130040100141000426692571046891107193750020300321000410004600441000410004400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026694441046979107201650010300201000010000600201000010000400011000040010
500241000536001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026694711046997107202950010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000601161001610017400071000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  ld1 { v0.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540228801311018003010080008300256188801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300641346801082008001220080012180000100
8020440059801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540291800451180034108000830640194800182080012208000018000010
8002440051800111180000108000030639982800102080000208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440060800111180000108000030640198800102080000208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440043800111180000108005930299127800692080071208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440055800111180000108000030640200800102080000208000018000010
8002440057800111180000108000030640384800102080000208006918000010
8002440052800111180000108000030639982800102080000208000018000010