Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 2D)

Test 1: uops

Code:

  ld1 { v0.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005294521003110021000300010001000100011000
61004292851001110001000300010001000100011000
61004292461001110001000300010001000100011000
61004292481001110001000300010001000100011000
61004292551001110001000300010001000100011000
61004292151001110001000300010001000100011000
61004292491001110001000300010001000100011000
61004292451001110001000300010001000100011000
61004292111001110001000300010001000100011000
61004292201001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001596010840101100061000130130100141000426691641045538107071950110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426694281045706107088050110302121000410004602241000410004400011000040100
502041000716010440101100031000030103100031000426691661045433107062650110302121000410004602241000410004400011000040100
502041000536010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000516010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000506010340101100021000030103100031001626712651046291107147350164302511001610017602241000410004400011000040100
502041000526010340101100021000030103100031000426692931045652107082550110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001546001840011100061000130040100141000426692581046891107193750020300321000410004600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001001526715861047900107294250074300701001710017601921002810030400131000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000601201001710017400071000040010
500241000776001340011100021000030010100001001426698911047123107218250072300681001610017600201000010000400011000040010
500241000546001340011100021000030010100001000026693631046946107198350010300201000010000600201000010000400011000040010
500241000506001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026692821046913107195050010300201000010000600201000010000400011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  ld1 { v0.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540188801311018003010080008300256242801082008001220080012180000100
8020440056801011018000010080008300640320801082008001220080012180000100
8020440056801011018000010080008300640410801082008001220080012180000100
8020440056801011018000010080008300640536801082008001220080014180000100
8020440068801051018000410080008300480188801082008001220080012180000100
8020440053801011018000010080008300640248801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540610800451180034108000830640248800182080012208001218000010
8002440054800111180000108000030640218800102080000208000018000010
8002440045800111180000108000030640218800102080000208000018000010
8002440051800111180000108000030640218800102080000208000018000010
8002440045800111180000108000030640218800102080000208006918000010
8002440045800111180000108000030640218800102080000208000018000010
8002440045800111180000108000030640218800102080000208007118000010
8002440053800111180000108000030640218800102080000208000018000010
8002440045800111180000108000030640218800102080000208000018000010
8002440045800111180000108000030640218800102080000208000018000010