Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 2S)

Test 1: uops

Code:

  ld1 { v0.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005293281003110021000300010001000100011000
61004291421001110001000300010001000100011000
61004291191001110001000300010001000100011000
61004290971001110001000300010001000100011000
61004291111001110001000300010001000100011000
61004291241001110001000300010001000100011000
61004291051001110001000300010001000100011000
61004293601001110001000300010001000100011000
61004292571001110001000300010001000100011000
61004291051001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5020510015060108401011000610001301301001410004266917610454881070674501103021210004100046022410004100044000110000040100
5020410004960103401011000210000301031000310004266907710455631070737501103021210004100046022410004100044000110000040100
5020410004260102401011000110000301031000310016267148310465671071719501643024610017100166022410004100044000110000040100
5020410004960103401011000210000301031000310004266950910457431070913501103021210004100046022410004100044000110000040100
5020410004260102401011000110000301031000310004266907710455631070737501103021210004100046022410004100044000110000040100
5020410004960103401011000210000301031000310004266910410455741070748501103021210004100046022410004100044000110000040100
5020410004960103401011000210000301031000310015267109410463811071660501643025010017100176022410004100044000110000040100
5020410004260102401011000110000301031000310004266903210454871070667501103021210004100046022410004100044000110000040100
5020410004260102401011000110000301031000310004266907710455631070737501103021210004100046022410004100044000110000040100
5020410004260102401011000110000301031000310004266926610456401070814501103021210004100046022410004100044000110000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001506001840011100061000130040100141000426692881046903107195050020300321000410004600201000010000400011000040010
500241000496001340011100021000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001001626696641047092107214850074300671001710016600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  ld1 { v0.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
802054015580131101080030100080008300640248801082008001220080012180000100
802054010880135101080034100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044004780101101080000100080008300640028801082008001220080012180000100
802044013980101101080000100080008300640190801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540257800451180034108000830640248800182080012208006918000010
8002440054800111180000108000030640470800102080000208000018000010
8002540118800451180034108000030641712800102080000208001218000010
8002440059800151180004108000030640164800102080000208000018000010
8002440051800111180000108000030248098800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010
8002440051800111180000108000030640164800102080000208000018000010