Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 4H)

Test 1: uops

Code:

  ld1 { v0.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005297101003110021000300010001000100011000
61004297761001110001000300010001000100011000
61004292581001110001000300010001000100011000
61004296821001110001000300010001000100011000
61004292031001110001000300310001000100011000
61004293121001110001000300010001000100011000
61004293261001110001000300010001000100011000
61004292451001110001000300010001000100011000
61004296891001110001000300310001000100011000
61004294921001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502041001066010340101100021000030103100031000426695281045727107090850110302121000410004602241000410004400011000040100
502041000506010340101100021000030103100031000426692211045564107074450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502051000816011240107100041000130133100151000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500251001566001840011100061000130040100141000426693121046913107195950020300321000410004600201000010000400011000040010
500241000496001340011100021000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001001526695181047033107207850073300691001610017600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000476001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000446001240011100011000030010100001001426700201047249107227350072300671001610017600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010
500251000746002140017100031000130043100151000026693361046935107197250010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026691471046858107189550010300201000010000600201000010000400011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  ld1 { v0.4h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540170801371018003610080008300399986801082008001220080012180000100
8020440051801051018000410080008300640012801082008001220080012180000100
8020440062801011018000010080008300640036801082008001220080012180000100
8020440060801011018000010080008300640082801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100
8020440047801011018000010080008300640028801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002640355800761180065108001030360028800202080014208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010
8002440045800111180000108000030639998800102080000208000018000010