Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 4S)

Test 1: uops

Code:

  ld1 { v0.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005293341003110021000300010001000100011000
61004291321001110001000300010001000100011000
61004291011001110001000300010001000100011000
61004292201001110001000300010001000100011000
61004295851001110001000300210001000100011000
61004291031001110001000300010001000100011000
61004291011001110001000300010001000100011000
61004291001001110001000300010001000100011000
61004291031001110001000300010001000100011000
61004291051001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001526010840101100061000130130100141000426692211045564107074450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031001626695741045748107092550164302501001710017602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031001626708701046288107146050164302501001710017602241000410004400011000040100
502051000816011240107100041000130133100161000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
500241000486001340011100021000030013100031000026692381046837107188050010300201000010000600201000010000400011000040010
500241000476001340011100021000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010
500251001286002140017100031000130043100151000026691201046847107188450010300201000010000600201000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000601181001610017400071000040010
500241000416001240011100011000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010
500241000426001240011100011000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000601141001610017400071000040010
500241000406001240011100011000030010100001000026690931046836107187350010300201000010000600201000010000400011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  ld1 { v0.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540194801351018003410080008300280188801082008001220080012180000100
8020440059801051018000410080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440125801011018000010080008300640302801082008001220080012180000100
8020440067801011018000010080008300640284801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100
8020440053801011018000010080008300640194801082008001220080012180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540370800451180034108000830269154800182080012208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440043800111180000108000030639982800102080000208000018000010
8002440044800111180000108005630366287800662080069208001418000010
8002440062800111180000107735811730363162484541992978037208000018000010
8002440050800111180000108000030640106800102080000208000018000010
8002440052800111180000108000030639990800102080000208000018000010
8002440045800111180000108000030639982800102080000208000018000010
8002440043800111180000108000030639982800102080000208000018000010