Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 1 reg, 8B)

Test 1: uops

Code:

  ld1 { v0.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
61005294331003110021000300010001000100011000
61004293311001110001000300010001000100011000
61004292841001110001000300210001000100011000
61004294261001110001001304110011001100011000
61004293131001110001000300010001000100011000
61004293041001110001000300010001000100011000
61004293101001110001000300010001000100011000
61004294271001110001000300010001000100011000
61004293441001110001000300010001000100011000
61004293041001110001000300010001000100011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
502051001556010840101100061000130130100141000426691731045484107067150110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041000496010340101100021000030103100031000426692661045640107081450110302121000410004602241000410004400011000040100
502041001466010340101100021000030103100031000426692121045618107079250110302121000410004602241000410004400011000040100
502041000406010240101100011000030103100031000426690771045563107073750110302121000410004602241000410004400011000040100
502051000726011040105100031000230133100151026326800491053824107164450763307641030410016602241000410004400011000040100
502041000506010340101100021000030103100031000426692211045564107074450110302121000410004602241000410004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004603001001710017400071000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602241000410004400011000040100
502041000476010340101100021000030103100031000426692121045618107079250110302121000410004602241000410004400011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
5002510015460018400111000610001300401001410004266924410468171071878500203003210004100046002010000100004000110000040010
5002410004860013400111000210000300101000010000266909310468361071873500103002010000100006002010000100004000110000040010
5002410004260012400111000110000300101000010000266909310468361071873500103002010000100006002010000100004000110000040010
5002410004060012400111000110000300101000010000266917410468691071906500103002010000100006002010000100004000110000040010
5002410004160012400111000110000300101000010000266909310468361071873500103002010000100006002010000100004000110000040010
5002410004360012400111000110000300101000010016266947510470211072073500743006710017100166002010000100004000110000040010
5002410004160012400111000110000300101000010000266909310468361071873500103002010000100006002010000100004000110000040010
5002410004360012400111000110000300101000010000266917410468721071906500103002010000100006002010000100004000110000040010
5002410004060012400111000110000300101000010000266912010468471071884500103002010000100006004410004100044000110000040010
5002410005360013400111000210000300101000010000266914710468581071895500103002010000100006002010000100004000110000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  ld1 { v0.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8020540192801371018003610080008300564996801082008001220080012180000100
8020440050801011018000010080008300640354801082008001220080012180000100
8020440045801011018000010080008300640102801082008001220080072180000100
8020440045801011018000010080008300640012801082008001220080012180000100
8020440168801381018003710080008300640012801082008001220080069180000100
8020440045801011018000010080106300351142802062008012820080012180000100
8020440045801011018000010080106300264442802062008012820080012180000100
8020440045801011018000010080008300640012801082008001220080128180000100
8020540098801381018003710080008300640012801082008001220080072180000100
8020441163803461018024510080251300400141803512028029720080411180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
8002540399800411180030108000830263018800182080012208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030640218800102080000208000018000010
8002440054800111180000108000030279778800102080000208000018000010