Icestorm: LD1 (multiple, 1 reg, 8H) measurements

Code:

  ld1 { v0.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 1.000

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	32168	1003	1	1002	1000	3000	1000	1000	1000	1	1000
61004	30094	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	29524	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	29573	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	29630	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	29563	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	29454	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	30424	1001	1	1000	1000	3000	1000	1000	1000	1	1000
61004	31115	1001	1	1000	1000	3005	1000	1000	1000	1	1000
61004	29525	1001	1	1000	1001	3003	1001	1001	1000	1	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100257	60108	40101	10006	10001	30130	10014	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100047	60103	40101	10002	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50205	100097	60112	40107	10004	10001	30133	10015	10004	2669168	1045542	1070722	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100040	60102	40101	10001	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50205	100070	60110	40105	10003	10002	30133	10015	10004	2669779	1045851	1071024	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100043	60102	40101	10001	10000	30103	10003	10004	2669212	1045618	1070792	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100041	60102	40101	10001	10000	30103	10003	10004	2669484	1045650	1070838	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100042	60102	40101	10001	10000	30103	10003	10004	2669266	1045640	1070814	50110	30212	10004	10004	60224	10004	10004	40001	10000	40100
50204	100130	60102	40101	10001	10000	30103	10003	10016	2671059	1046392	1071545	50169	30250	10017	10017	60298	10016	10017	40009	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100147	60018	40011	10006	10001	30040	10014	10000	2669237	1046837	1071880	50010	30020	10000	10000	60096	10012	10013	40009	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10024	2672388	1048124	1073226	50126	30097	10024	10026	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10014	2669669	1047096	1072128	50072	30067	10016	10017	60020	10000	10000	40001	10000	40010
50024	100047	60013	40011	10002	10000	30010	10000	10000	2669282	1046913	1071950	50010	30020	10000	10000	60020	10000	10000	40001	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]
  ld1 { v0.8h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 0.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	40183	80135	101	80034	100	80008	300	640572	80108	200	80012	200	80012	1	80000	100
80204	40062	80105	101	80004	100	80008	300	642318	80108	200	80012	200	80012	1	80000	100
80204	40059	80101	101	80000	100	80008	300	640392	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	640248	80108	200	80012	200	80012	1	80000	100
80204	40056	80101	101	80000	100	80008	300	645666	80108	200	80012	200	80012	1	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 0.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	40418	80041	11	80030	10	80008	30	421968	80018	20	80012	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639998	80010	20	80000	20	80000	1	80000	10
80024	40046	80011	11	80000	10	80000	30	640312	80010	20	80000	20	80014	1	80000	10
80024	40047	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40045	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40044	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10
80024	40043	80011	11	80000	10	80000	30	639982	80010	20	80000	20	80000	1	80000	10

LD1 (multiple, 1 reg, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations