Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 16B)

Test 1: uops

Code:

  ld1 { v0.16b, v1.16b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005297812005120042000600020002000200012000
62005296902003120022000600020002000200012000
62004296992001120002000600020002000200212000
62004296402001120002000600620002000200012000
62004297082001120002000600020002000200012000
62004293792001120002000600020002000200012000
62004297332001120002000600020002000200012000
62004300552001120002000600220002000200012000
62004295532001120002000600020002000200012000
62004295452001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.16b, v1.16b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001507010940101100062000230130100152000426691931779374104851060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602051000827011440108100042000230134100142000426695031779616104868060110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426692601779454104858160110302122000810004602242000810004400012000040100
602041000747010440101100032000030103100032000426691381779298104844360110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602862002810015400082000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001507001940011100062000230040100152000426719561781156105058860020300322000810004600202000010000400012000040010
600241000527001340011100022000030010100002000026693841779446104954460010300202000010000601062002810015400082000040010
600241000467001240011100012000030013100032000426691631779290104944760020300322000810004600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002002426695721779592104961760082300652002810015600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002008026764531784104105229360262301482008010044600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.16b, v1.16b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001557010940101100062000230130100152000426691811779362104850360110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602051000757011540110100032000230135100132000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426691251779364104852660110302122000810004602242000810004400012000040100
602041000447010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690711779328104850460110302122000810004602242000810004400012000040100
602041000437010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001547001940011100062000230040100152000426692691779400104953760020300322000810004600202000010000400012000040010
600241000407001240011100012000030010100002000026713011780724105032560010300202000010000602802008010044400372000040010
600241000427001240011100012000030010100002002026706071780244105000360074300532002010011601482004010022400192000040010
600241000407001240011100012000030010100002004026722201781302105062860138300862004010022601482004010022400192000040010
600241000407001240011100012000030010100002002026705151780190104997660072300512002010011601022002810015400082000040010
600241000477001340011100022000030010100002020327126391808154107542660637303372020310107613722042110230401892000040010
600241037777029440169100532007230582101962000026691141779266104943460010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  ld1 { v0.16b, v1.16b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1602058018016013510101600341000160008300496242016010820016001202001600121160000100
16020580111160131101016003010001600083001135800016010820016001202001600121160000100
16020480056160101101016000010001600083001280248016010820016001202001600121160000100
16020480056160101101016000010001600083001280248016010820016001202001600121160000100
16020480365160101101016000010001600083001280608016010820016001202001600121160000100
16020480059160101101016000010001600083001280248016010820016001202001600121160000100
16020480064160101101016000010001600083001280248016010820016001202001600121160000100
16020480056160101101016000010001600083001280464016010820016001202001600121160000100
16020480062160101101016000010001600083001280248016010820016001202001600121160000100
10447973589103481528932981605012291600083001280248016010820016001202001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002580210160045111600341016000830800476160018201600122016001201160000010
16002480054160011111600001016005630606908160066201600682016000001160000010
160024800541600111116000010160000301280218160010201600002016006801160000010
160024800541600111116000010160000301280218160010201600002016000001160000010
160024800541600111116000010160000301280218160010201600002016000001160000010
160024800541600111116000010160000301280218160010201600002016000001160000010
160024800541600111116000010160000301286734160010201600002016000001160000010
160024800811600111116000010160000301280326160010201600002016000001160000010
160024800541600111116000010160000301280218160010201600002016000001160000010
160024800541600111116000010160000301280218160010201600002016006801160000010