Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 1D)

Test 1: uops

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005298292005120042000600020002000200012000
62004294682001120002000600020002000200012000
62004294252001120002000600020002000200012000
62004294672001120002000600020002000200012000
62004294622001120002000600020002000200012000
62004294752001120002000600020002000200012000
62004294332001120002000600020002000200012000
62004294642001120002000600020002000200012000
62004294652001120002000600020002000200012000
62004294352001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001507010940101100062000230130100152000426691931779374104851060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000727010440101100032000030103100032000426690841779262104842160110302122000810004602242000810004400012000040100
602051001287011540108100052000230134100142000426692331779436104857060110302122000810004602862002810015400082000040100
602041000507010340101100022000030103100032000426719331781236104967060110302122000810004602242000810004400012000040100
602041000517010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602051001497011440105100052000430133100132000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002510015370019400111000620002300401001520004266928317793741049499600203003220008100046004420008100044000120000040010
6002410004970013400111000220000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006010220028100154000820000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006010220028100154000820000040010
6002410004470012400111000120000300101000020024266949117795381049585600823006120028100156002020000100004000120000040010
6002410004270012400111000120000300101000020000266911417792661049434600103002020000100006002020000100004000120000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051002587010940101100062000230130100152000426689401779162104835860110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602822002810014400092000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000437010240101100012000030103100032002426696501779708104870760172302412002810015602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251002857001940011100062000230040100152000426692831779374104949960020300322000810004600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000601102002810015400082000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  ld1 { v0.1d, v1.1d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205802101601351011600341001600083005121881601082001600122001600121160000100
1602048029916010110116000010016000830012812561601082001600122001600121160000100
1602048005916010110116000010016000830012801941601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600121160000100
160204800531601011011600001001600083009601881601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600121160000100
1602048005316010110116000010016000830012801941601082001600122001600681160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160025802001600451116003410160008308001121600182016001220160000116000010
1600258010016004711160036101600083012803381600182016001220160012116000010
1600248004816001111160000101600003012800361600102016000020160000116000010
1600248004316001111160000101600003012821801600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600563012159921600662016006820160000116000010
1600248005216001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010