Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 2D)

Test 1: uops

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005317682005120042000600020002000200012000
62004294722001120002000600020002000200012000
62004294582001120002000600020002000200012000
62004294202001120002000600020002000200012000
62004294922001120002000600020002000200012000
62004295042001120002000600020002000200012000
62004294412001120002000600020002000200012000
62004294852001120002000600020002000200012000
62004296432001120002000600020002000200012000
62004297332001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001557010940101100062000230130100152000426690871779264104842160110302122000810004602902002810015400082000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000567010340101100022000030103100032000426693141779490104860360110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032002426695391779632104865860172302412002810015602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600261001887003040018100082000430071100262000426693231779436104955960020300322000810004600202000010000400012000040010
600241000557001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000557001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000601022002810015400082000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000577001340011100022000030010100002000026694111779464104955560010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020510014970109401011000620002301301001520004266914117793001048443601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320024267179117811341049576601723024320028100156022420008100044000120000040100
6020410004970103401011000220000301031000320004266926017794541048581601103021220008100046022420008100044000120000040100
6020410004970103401011000220000301031000320004266923317794361048570601103021220008100046022420008100044000120000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251005167001940011100062000230040100152000026691971779282104942160010300202000010000600202000010000400012000040010
600241000567001340011100022000030010100002000026693301779410104952260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600251000737002340018100032000230044100142000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  ld1 { v0.2d, v1.2d }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205801701601351011600341001600083001280194016010820016001202001600121160000100
16020480053160101101160000100160008300560006016010820016001202001600121160000100
160205800981601371011600361001600083001281470016010820016001202001600121160000100
160204800451601011011600001001600083001280156016010820016001202001600121160000100
160204800571601011011600001001600083001280082016010820016001202001600121160000100
160204800451601011011600001001600083001280012016010820016001202001600121160000100
160204800451601011011600001001600083001280012016010820016001202001600121160000100
160204800451601011011600001001600083001280012016010820016001202001600121160000100
160204800451601011011600001001600083001280012016010820016001202001600121160000100
160204800451601011011600001001600083001280012016010820016001202001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16002580186160045111600341016000830520908016001820160012020160000116000010
160024800511600111116000010160000301280164016001020160000020160000116000010
160024800511600111116000010160000301280164016001020160000020160000116000010
160024800511600111116000010160000301280164016001020160000020160000116000010
160024800511600111116000010160056301178784016006620160068020160000116000010
160024800511600111116000010160000301280164016001020160000020160000116000010
160024800511600111116000010160000301280164016001020160000020160000116000010
160024800511600111116000010160000301280164016001020160000020160068116000010
160024801511600111116000010160000301280650016001020160000020160000116000010
160024800541600111116000010160000301280218016001020160000020160000116000010