Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 2S)

Test 1: uops

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005297812005120042000600020002000200012000
62004295862001120002000600020002000200012000
62004296522001120002000600820002000200012000
62004299662001120002000600020002000200012000
62004294142001120002000600020002000200012000
62004294112001120002000600020002000200012000
62004294132001120002000600020002000200012000
62004293992001120002000600020002000200012000
62004293922001120002000600020002000200012000
62004294232001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001547010940101100062000230130100152000426690871779264104842160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691271779326104848160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000567010340101100022000030103100032000426693411779508104861460110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602822002810015400082000040100
602041000537010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602061001987012740115100082000430165100252000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426692601779454104858160110302122000810004602242000810004400012000040100
602041000487010340101100022000030103100032000426691791779400104854860110302122000810004602902002810015400082000040100
602041000497010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001507001940011100062000230040100152000426693231779436104955960020300322000810004600202000010000400012000040010
600241000497001340011100022000030010100002002426713001780744105031960082300652002810015600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693301779410104952260010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600251000827002440018100042000230044100142000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020510015270109401011000620002301301001520004266908717792641048421601103021220008100046022420008100044000120000040100
6020410004070102401011000120000301031000320004266909817793461048515601103021220008100046022420008100044000120000040100
6020410004070102401011000120000301031000320024267207717813241049690601723024520028100156022420008100044000120000040100
6020510015370113401081000320002301341001420024267134817808381049391601723024120028100156022420008100044000120000040100
6020510015270114401081000420002301341001420004266901717792921048482601103021220008100046035620048100264001520000040100
6020510016470114401081000420002301341001420024267135717808441049391601723024520028100156022420008100044000120000040100
6020410004070102401011000120000301031000320004266899017792741048471601103021220008100046028820032100164000520000040100
6020410004070102401011000120000301031000320024267234717815041049793601723024520028100156029020028100154000820000040100
6020410004070102401011000120000301031000320024275456718363181115259601723024420028100156022420008100044000120000040100
6020410004070102401011000120000301031000320004266899017792741048471601103021220008100046028220028100154000820000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600261001847003040018100082000430071100262000426691091779254104942560020300322000810004600202000010000400012000040010
600241001517002940020100052000430043100112002026706081780252105001460072300512002010011600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000457001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000601022002810015400082000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691951779320104946760010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000437001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  ld1 { v0.2s, v1.2s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205802711601311011600301001600083006722421601082001600122001600121160000100
1602048005616010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100
1602058009816013510116003410016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012854821601082001600122001600121160000100
1602048007116010110116000010016000830012801181601082001600122001600121160000100
1602048004716010110116000010016005630011646261601562001600682001600121160000100
1602048004716010110116000010016000830012801361601082001600122001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
1600258019216004511016003410016000830800242160018201600122016001201160000010
16002480056160011110160000100160008301280248160018201600122016001201160000010
16002480056160011110160000100160008301280248160018201600122016001201160000010
16002480056160011110160000100160008301280248160018201600122016001201160000010
16002480245160011110160000100160008301280302160018201600122016001201160000010
16002480056160011110160000100160008301280248160018201600122016001201160000010
16002480094160011110160000100160008301280302160018201600122016001201160000010
16002480062160015110160004100160000301279982160010201600002016000001160000010
16002480043160011110160000100160000301279982160010201600002016000001160000010
16002480043160011110160000100160000301279982160010201600002016000001160000010