Icestorm: LD1 (multiple, 2 regs, 4H) measurements

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29808	2003	1	2002	2000	6002	2000	2000	2000	1	2000
62004	29445	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29607	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29609	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29581	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29529	2001	1	2000	2000	6000	2000	2000	2006	1	2000
62004	29512	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29428	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29604	2001	1	2000	2000	6000	2000	2000	2000	1	2000
62004	29403	2001	1	2000	2000	6000	2000	2000	2000	1	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100153	70109	40101	10006	20002	30130	10015	20004	2669193	1779374	1048510	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60205	100140	70114	40108	10004	20002	30134	10014	20004	2669233	1779436	1048570	60110	30212	20008	10004	60286	20028	10015	40008	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100049	70103	40101	10002	20000	30103	10003	20004	2669233	1779436	1048570	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
60025	100151	70019	40011	10006	20002	30040	10015	20000	2669251	1779318	1049443	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20024	2669491	1779538	1049586	60082	30061	20028	10015	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2671274	1780706	1050314	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100046	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669897	1779788	1049753	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100044	70012	40011	10001	20000	30010	10000	20000	2669222	1779338	1049478	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60025	100075	70023	40018	10003	20002	30044	10014	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010
60024	100042	70012	40011	10001	20000	30010	10000	20000	2669114	1779266	1049434	60010	30020	20000	10000	60020	20000	10000	40001	20000	0	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100150	70109	40101	10006	20002	30130	10015	20004	2669084	1779262	1048420	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60290	20028	10015	40008	20000	40100
60204	100070	70104	40101	10003	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60284	20028	10015	40008	20000	40100
60204	100070	70104	40101	10003	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100
60204	100047	70103	40101	10002	20000	30103	10003	20004	2669179	1779400	1048548	60110	30212	20008	10004	60224	20008	10004	40001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60026	100186	70030	40018	10008	20004	30071	10026	20440	2679630	1783769	1050380	61089	30864	20503	10015	60044	20008	10004	40001	20000	40010
60024	100047	70013	40011	10002	20000	30010	10000	20000	2669249	1779356	1049489	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100070	70014	40011	10003	20000	30013	10003	20000	2669263	1779330	1049451	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20024	2672164	1781320	1050680	60082	30061	20028	10015	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010
60024	100049	70013	40011	10002	20000	30010	10000	20000	2669303	1779392	1049511	60010	30020	20000	10000	60020	20000	10000	40001	20000	40010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]
  ld1 { v0.4h, v1.4h }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80172	160131	101	160030	100	160008	300	512188	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	202	160070	2	160000	100
160204	80055	160101	101	160000	100	160008	300	1284244	160108	200	160012	200	160012	1	160000	100
160204	80062	160105	101	160004	100	160008	300	1280082	160108	200	160012	200	160012	1	160000	100
160204	80081	160101	101	160000	100	160008	300	560006	160108	200	160012	200	160068	1	160000	100
160204	80053	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100
160204	80045	160101	101	160000	100	160008	300	1280012	160108	200	160012	200	160012	1	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80178	160045	11	0	160034	10	0	160008	30	800188	160018	20	160012	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160056	30	799854	160066	20	160068	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160000	30	1280164	160010	20	160000	20	160000	1	160000	10
160024	80073	160011	11	0	160000	10	0	160000	30	1281100	160010	20	160000	20	160000	1	160000	10
160024	80051	160011	11	0	160000	10	0	160056	30	500464	160066	20	160068	20	160000	1	160000	10

LD1 (multiple, 2 regs, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations