Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 4S)

Test 1: uops

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005345282005120042000600020002000200012000
62004294192001120002000600020002000200012000
62004294082001120002000600020002000200012000
62004293692001120002000600020002000200012000
62004293722001120002000600020002000200012000
62004293862001120002000600020002000200012000
62004294002001120002000600220002000200012000
62004294262001120002000600020002000200012000
62004293812001120002000600020002000200012000
62004293642001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001567010940101100062000230130100152000426691271779326104848160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426713661780858104943660110302122000810004602242000810004400012000040100
602041000517010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602051000877011540108100052000230134100142002426702141780082104893260172302452002810015602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426692871779472104859260110302122000810004602242000810004400012000040100
602041000487010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001477001940011100062000230040100152000426692691779400104953760020300322000810004600202000010000400012000040010
600241000477001340011100022000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000601022002810015400082000040010
600241000497001340011100022000030013100032000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600251000947002340018100032000230044100142000026691681779302104945660010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001557010940101100062000230130100152000426691391779338104848860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602051000737011340108100032000230134100142000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100
602041000407010240101100012000030103100032000426689901779274104847160110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6002510032870019400111000620002300401001520004266913417793101049482600203003220008100046004420008100044000120000040010
6002410004570012400111000120000300101000020000266919517793201049467600103002020000100006011020028100154000820000040010
6002410005070013400111000220000300131000320000266920917792941049429600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006011020028100154000820000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020000266906017792301049412600103002020000100006002020000100004000120000040010
6002410004070012400111000120000300101000020024267143517808341050384600823006520028100156002020000100004000120000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  ld1 { v0.4s, v1.4s }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160205801691601351011600341001600083004961881601082001600122001600121160000100
1602048013616010110116000010016000830012804081601082001600122001600121160000100
1602048004516010110116000010016005630012445941601562001600682001600121160000100
1602048004816010110116000010016000830012800121601082001600122001600121160000100
1602048004516010110116000010016000830012800121601082001600122001600121160000100
1602048004516010110116000010016000830012864761601082001600122001600121160000100
1602048005916010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100
1602048004716010110116000010016000830012800281601082001600122001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600258018016004511160034101600083012800121600182016001220160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160068116000010
1600248004316001111160000101600003012799821600102016000020160068116000010
1600248008116001111160000101600003012800981600102016000020160000116000010
1600248005016001111160000101600003012799821600102016000020160000116000010
1600248004316001111160000101600003012801801600102016000020160000116000010
1600248004316001111160000101600003012799821600102016000020160000116000010