Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 8B)

Test 1: uops

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005296842005120042000600020002000200012000
62004300642001120002000600020002000200012000
62004297652001120002000600020002000200012000
62004295372001120002000600020002000200012000
62004295142001120002000600020002000200012000
62004305332001120002000600020002000200012000
62004293022001120002000600020002000200012000
62004293032001120002000600020002000200012000
62004293022001120002000600020002000200012000
62004293532001120002000600020002000200012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001527010940101100062000230130100152000426690841779262104842160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032002426695361779628104864060172302422002810014602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000517010340101100022000030103100032000426692601779454104858160110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426691901779372104851060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000497010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100
602041000507010340101100022000030103100032000426692331779436104857060110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001527001940011100062000230040100152000426690401779212104940060020300322000810004600202000010000400012000040010
600241000547001240011100012000030010100002000026691411779284104944560010300202000010000600202000010000400012000040010
600251000737002340018100032000230044100142000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000601022002810015400082000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026690601779230104941260010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602061002697012040108100082000430161100262002427031901801987107452360173302452002910015602242000810004400012000040100
602051001117011340108100032000230134100142000426692331779436104857060110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690981779346104851560110302122000810004602242000810004400012000040100
602041000457010240101100012000030103100032000426691251779364104852660110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602051000757011340108100032000230134100142000426692331779436104857060110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100
602041000427010240101100012000030103100032000426690441779310104849360110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251003097001940011100062000230040100152000426692291779338104947260020300302000810004600442000810004400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002002026711741780622105023660074300532002010011600202000010000400012000040010
600241001507001440011100032000030010100002002426714501780842105039060082300612002810015600202000010000400012000040010
600241000407001240011100012000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000507001240011100012000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241001427002840020100042000430043100112000026693301779410104952260010300202000010000600202000010000400012000040010
600241000407001240011100012000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  ld1 { v0.8b, v1.8b }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020580179160131101160030100160008300560242160108200160012200160012011600000100
160204800621601011011600001001600083001280356160108200160012200160012011600000100
160204800681601011011600001001600083001280302160108200160012200160012011600000100
160204800671601011011600001001600083001280302160108200160012200160012011600000100
160204800561601011011600001001600083001280248160108200160012200160012011600000100
160204800561601011011600001001600563001231448160156200160068200160012011600000100
160204801121601011011600001001600083001280788160108200160012200160012011600000100
160204800561601011011600001001600083001280248160108200160012200160012011600000100
160204800561601011011600001001600083001280248160108200160012200160012011600000100
160204800561601011011600001001600083001280248160108200160012200160012011600000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002580184160045111600341016000030101114801600102016000002016012401160000010
16002480055160011111600001016000030128030801600102016000002016000001160000010
16002480059160011111600001016000030128021801600102016000002016000001160000010
16002480054160011111600001016000030128016401600102016000002016000001160000010
16002480051160011111600001016000030128016401600102016000002016000001160000010
16002480051160011111600001016000030128016401600102016000002016000001160000010
16002480051160011111600001016000030128016401600102016000002016000001160000010
16002480051160011111600001016000030128016401600102016000002016006801160000010
16002480062160011111600001016000030128025401600102016000002016000001160000010
16002480056160011111600001016000030128016401600102016000002016000001160000010