Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, 2 regs, 8H)

Test 1: uops

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.000

Integer unit issues: 0.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch ldst uop (58)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
62005298232005120042000600020002000200012000
62004296822001120002000600020002000200012000
62004294952001120002000600020002000200012000
62004294492001120002000600020002000200012000
62004295552001120002000600220002000200012000
62004295202001120002000600020002000200012000
62004297412001120002000600020002000200012000
62004295342001120002000600220002000200012000
62004293382001120002000600020002000200012000
62004293332001120002000600020002000200212000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
602051001517010940101100062000230130100152000426691291779288104843560110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426692711779426104854360110302122000810004604162006810037400292000040100
602041004107016940137100122002030227100472000426691271779326104848160110302122000810004602882002810015400082000040100
602051001487011440108100042000230134100142000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426693681779526104862560110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100
602041000477010340101100022000030103100032000426691791779400104854860110302122000810004602242000810004400012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001557001940011100062000230040100152002426695861779566104957860082300612002810015600442000810004400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000600202000010000400012000040010
600241000477001340011100022000030010100002000026692491779356104948960010300202000010000601022002810015400082000040010
600241000497001340011100022000030013100032000426693231779436104955960020300322000810004600442000810004400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026693031779392104951160010300202000010000600202000010000400012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
6020510015170109401011000620002301301001520004266930117794461048554601103021220008100046022420008100044000120000040100
6020410004770103401011000220000301031000320004266899017792741048471601103021220008100046022420008100044000120000040100
6020410006170103401011000220000301031000320004266917917794001048548601103021220008100046022420008100044000120000040100
6020410004070102401011000120000301031000320004266899017792741048471601103021220008100046022420008100044000120000040100
6020410004070102401011000120000301031000320004266899017792741048471601103021220008100046022420008100044000120000040100
6020410004270102401011000120000301031000320004266931417794901048603601103021220008100046028220028100154000820000040100
6020510318670113401081000320002301341001420004266893817792001048404601103021220008100046029020028100154000820000040100
6020410005470103401011000220000301031000320004266896517792181048415601103021220008100046022420008100044000120000040100
6020410004170102401011000120000301031000320024266935017795061048579601723024120028100156022420008100044000120000040100
6020510016370114401081000420002301341001420004266926017794541048581601103021220008100046022420008100044000120000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
600251001517001940011100062000230040100152000026693031779392104951160010300202000010000600202000010000400012000040010
600241000497001340011100022000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600251003097002440018100042000230044100142000026692631779330104945060010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010
600241000427001240011100012000030010100002000026691141779266104943460010300202000010000600202000010000400012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  ld1 { v0.8h, v1.8h }, [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020580230160131101160030100160008300672206016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
16020480053160101101160000100160056300610942016015620016006802001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100
160204800531601011011600001001600083001280194016010820016001202001600121160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
1600258059616004111160030101600083012547021600182016001220160000116000010
1600248005416001111160000101600003012802181600102016000020160000116000010
1600248005416001111160000101600003012802181600102016000020160000116000010
1600248005416001111160000101600003012802181600102016000020160000116000010
1600258011116004111160030101600003012802181600102016000020160000116000010
1600248005416001111160000101600003012802181600102016000020160068116000010
1600248014816001111160000101600003012803801600102016000020160000116000010
1600248005916001111160000101600003012803261600102016000020160000116000010
1600248005416001111160000101600003012802181600102016000020160068116000010
160024801551600111116000010160008309240941600182016001220160000116000010