Icestorm: LD1 (multiple, 3 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 3.000

Integer unit issues: 0.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
63006	30333	3007	1	3006	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29729	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29699	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29693	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29701	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29704	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	29697	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	31115	3001	1	3000	3000	9009	3000	3000	0	3000	0	1	3000	0	0
63004	29739	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0
63004	30013	3001	1	3000	3000	9000	3000	3000	0	3000	0	1	3000	0	0

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]
  ld1 { v0.2d, v1.2d, v2.2d }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120188	240131	101	0	240030	100	0	240008	300	768014	240108	200	240012	200	240068	1	240000	100
240204	120076	240101	101	0	240000	100	0	240008	300	1920066	240108	200	240012	200	240012	1	240000	100
240204	120045	240101	101	0	240000	100	0	240008	300	1920012	240108	200	240012	200	240012	1	240000	100
240204	120045	240101	101	0	240000	100	0	240008	300	1920012	240108	200	240012	200	240012	1	240000	100
240205	120372	240131	101	0	240030	100	0	240008	300	1920192	240108	200	240012	200	240012	1	240000	100
240204	120045	240101	101	0	240000	100	0	240008	300	1920012	240108	200	240012	200	240068	1	240000	100
240204	120063	240101	101	0	240000	100	0	240008	300	1920426	240108	200	240012	200	240068	1	240000	100
176740	98673	176683	1855	4	174824	1676	4	240107	307	1851060	240209	202	240125	200	240012	1	240000	100
240204	120075	240101	101	0	240000	100	0	240008	300	1920102	240108	200	240012	200	240012	1	240000	100
240204	120045	240101	101	0	240000	100	0	240008	300	1920012	240108	200	240012	200	240012	1	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
240025	120176	240045	11	0	240034	10	0	240008	30	1200188	240018	20	240012	20	240000	1	240000	0	10
240024	120051	240011	11	0	240000	10	0	240000	30	1920164	240010	20	240000	20	240000	1	240000	0	10
240024	120051	240011	11	0	240000	10	0	240000	30	1920164	240010	20	240000	20	240000	1	240000	0	10
240025	120104	240045	11	0	240034	10	0	240000	30	1920164	240010	20	240000	20	240000	1	240000	0	10
240024	120051	240011	11	0	240000	10	0	240000	30	1920164	240010	20	240000	20	240000	1	240000	0	10
240024	120463	240011	11	0	240000	10	0	240192	30	1627985	240202	20	240223	995	240872	436	240380	3	572
240024	120293	240071	11	0	240060	10	0	240107	30	1542989	240117	20	240128	20	240000	1	240000	0	10
240024	120285	240071	11	0	240060	10	0	240096	30	949340	240106	20	240113	20	240112	1	240000	0	10
240024	121673	240401	11	0	240390	10	0	240008	30	960188	240018	20	240012	20	240000	1	240000	0	10
240024	120051	240011	11	0	240000	10	0	240000	30	1920164	240010	20	240000	20	240068	1	240000	0	10

LD1 (multiple, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations