Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 63005 | 29696 | 3007 | 1 | 3006 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29381 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29369 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29369 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29352 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3003 | 1 | 3000 |
| 63004 | 29367 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29374 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29358 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29371 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29382 | 3001 | 1 | 3000 | 3000 | 0 | 9000 | 3000 | 0 | 3000 | 3000 | 1 | 3000 |
Count: 8
Code:
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]
ld1 { v0.4h, v1.4h, v2.4h }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.5007
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240205 | 120182 | 240135 | 101 | 240034 | 100 | 240008 | 300 | 744242 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120062 | 240105 | 101 | 240004 | 100 | 240008 | 300 | 1440242 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 1927160 | 0 | 240108 | 200 | 240012 | 0 | 202 | 240238 | 2 | 240000 | 100 |
| 240204 | 120569 | 240227 | 101 | 240126 | 100 | 240059 | 300 | 1063373 | 0 | 240159 | 200 | 240072 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 1920446 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120070 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 1920248 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 1920248 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240068 | 1 | 240000 | 100 |
| 240204 | 120166 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 1920428 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 240000 | 100 | 240008 | 300 | 840242 | 0 | 240108 | 200 | 240012 | 0 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120298 | 240168 | 101 | 240067 | 100 | 240106 | 300 | 1014930 | 0 | 240206 | 200 | 240124 | 0 | 200 | 240123 | 1 | 240000 | 100 |
Result (median cycles for code divided by count): 1.5007
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240025 | 120305 | 240041 | 11 | 240030 | 10 | 240008 | 30 | 1920012 | 240018 | 20 | 240012 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120055 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920144 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120076 | 240011 | 11 | 240000 | 10 | 240008 | 30 | 1415870 | 240018 | 20 | 240012 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120060 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920326 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240068 | 1 | 240000 | 10 |
| 240024 | 120045 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |