Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 3.000
Issues: 3.000
Integer unit issues: 0.001
Load/store unit issues: 3.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 63005 | 30009 | 3019 | 1 | 3018 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29337 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29412 | 3001 | 1 | 3000 | 3000 | 9002 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29341 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29367 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29337 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29338 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29338 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
| 63004 | 29336 | 3001 | 1 | 3000 | 3000 | 9006 | 3000 | 3000 | 3003 | 1 | 3000 |
| 63004 | 29770 | 3001 | 1 | 3000 | 3000 | 9000 | 3000 | 3000 | 3000 | 1 | 3000 |
Count: 8
Code:
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]
ld1 { v0.8b, v1.8b, v2.8b }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 1.5007
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule simd uop (54) | schedule ldst uop (55) | dispatch int uop (56) | dispatch simd uop (57) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240205 | 120176 | 240135 | 101 | 0 | 240034 | 100 | 0 | 240008 | 300 | 744242 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240056 | 300 | 1422758 | 240156 | 200 | 240068 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240008 | 300 | 1920248 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120109 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240008 | 300 | 1920338 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240056 | 300 | 1925494 | 240156 | 200 | 240068 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120066 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240008 | 300 | 1920248 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120059 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240059 | 300 | 1924874 | 240159 | 200 | 240071 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240008 | 300 | 1920248 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240204 | 120056 | 240101 | 101 | 0 | 240000 | 100 | 0 | 240008 | 300 | 1920464 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
| 240205 | 120380 | 240131 | 101 | 0 | 240030 | 100 | 0 | 240008 | 300 | 1920284 | 240108 | 200 | 240012 | 200 | 240012 | 1 | 240000 | 100 |
Result (median cycles for code divided by count): 1.5006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 240026 | 120588 | 240071 | 11 | 240060 | 10 | 240059 | 30 | 960674 | 240069 | 20 | 240072 | 20 | 240012 | 1 | 240000 | 10 |
| 240025 | 120400 | 240041 | 11 | 240030 | 10 | 240000 | 30 | 1920326 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240057 | 1 | 240000 | 10 |
| 240024 | 120060 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240072 | 1 | 240000 | 10 |
| 240024 | 120060 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240068 | 1 | 240000 | 10 |
| 240025 | 120123 | 240048 | 11 | 240037 | 10 | 240056 | 30 | 1514558 | 240066 | 20 | 240068 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240056 | 30 | 1728698 | 240066 | 20 | 240068 | 20 | 240068 | 1 | 240000 | 10 |
| 240024 | 120057 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240025 | 120121 | 240047 | 11 | 240036 | 10 | 240000 | 30 | 1924646 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |
| 240024 | 120054 | 240011 | 11 | 240000 | 10 | 240000 | 30 | 1920218 | 240010 | 20 | 240000 | 20 | 240000 | 1 | 240000 | 10 |