Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.001
Load/store unit issues: 4.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | simd uops in schedulers (5a) | dispatch uop (78) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 64005 | 30380 | 4009 | 1 | 4008 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 30042 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29769 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29697 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29977 | 4001 | 1 | 4000 | 4000 | 12012 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64005 | 30480 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29480 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29483 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29477 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
| 64004 | 29484 | 4001 | 1 | 4000 | 4000 | 12000 | 4000 | 4000 | 0 | 4000 | 1 | 4000 | 0 | 0 |
Count: 8
Code:
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]
ld1 { v0.1d, v1.1d, v2.1d, v3.1d }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0007
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | map simd uop inputs (81) | ? int output thing (e9) | ? ldst retires (ed) | ? simd retires (ee) | ? int retires (ef) |
| 320205 | 160167 | 320137 | 101 | 320036 | 100 | 320058 | 300 | 1352030 | 320158 | 200 | 320072 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160065 | 320107 | 101 | 320006 | 100 | 320058 | 300 | 2430762 | 320158 | 200 | 320072 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320205 | 160386 | 320131 | 101 | 320030 | 100 | 320010 | 300 | 2560260 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320205 | 160355 | 320131 | 101 | 320030 | 100 | 320010 | 300 | 2560368 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160057 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560368 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160068 | 320101 | 101 | 320000 | 100 | 320058 | 300 | 2316798 | 320158 | 200 | 320072 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160057 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560260 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160057 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560260 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160558 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560368 | 320110 | 200 | 320016 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
| 320204 | 160071 | 320101 | 101 | 320000 | 100 | 320058 | 300 | 1949652 | 320158 | 200 | 320072 | 200 | 320016 | 0 | 1 | 320000 | 0 | 100 |
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 320025 | 160184 | 320041 | 11 | 320030 | 10 | 320000 | 30 | 1279998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160045 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160045 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160048 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2560664 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160054 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2560466 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320025 | 160382 | 320041 | 11 | 320030 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160045 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320025 | 160094 | 320041 | 11 | 320030 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160073 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2560160 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160045 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559998 | 320010 | 20 | 320000 | 20 | 320056 | 1 | 320000 | 10 |