Apple Microarchitecture Research by Dougall Johnson M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions M1/A14 E-core (Icestorm): Overview | Base Instructions | SIMD and FP Instructions
Code:
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nopmov x0, 1 mov x1, 2 mov x8, 0
(no loop instructions)
Retires (minus 60 nops): 4.000
Issues: 4.000
Integer unit issues: 0.001
Load/store unit issues: 4.000
SIMD/FP unit issues: 0.000
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | ldst uops in schedulers (5b) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map simd uop (7e) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) |
| 64005 | 31150 | 4009 | 1 | 4008 | 4000 | 0 | 12002 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 30228 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29994 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 30278 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29660 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29642 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29731 | 4001 | 1 | 4000 | 4000 | 0 | 12030 | 0 | 4000 | 0 | 4000 | 0 | 4002 | 1 | 4000 |
| 64004 | 29759 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29606 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
| 64004 | 29609 | 4001 | 1 | 4000 | 4000 | 0 | 12000 | 0 | 4000 | 0 | 4000 | 0 | 4000 | 1 | 4000 |
Count: 8
Code:
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]
ld1 { v0.2d, v1.2d, v2.2d, v3.2d }, [x6]mov x7, x6 mov x8, x6 mov x9, x6 mov x10, x6 mov x11, x6 mov x12, x6 mov x13, x6
(fused SUBS/B.cc loop)
Result (median cycles for code divided by count): 2.0007
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 320205 | 160163 | 320131 | 101 | 320030 | 100 | 320010 | 300 | 992248 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160115 | 320101 | 101 | 320000 | 100 | 320106 | 300 | 2359832 | 320206 | 200 | 320128 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160066 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560314 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320205 | 160362 | 320131 | 101 | 320030 | 100 | 320058 | 300 | 2057208 | 320158 | 200 | 320072 | 200 | 320072 | 1 | 320000 | 100 |
| 320204 | 160073 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 1120194 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160054 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560206 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160054 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560206 | 320110 | 200 | 320016 | 200 | 320072 | 1 | 320000 | 100 |
| 320204 | 160054 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560206 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160054 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560206 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
| 320204 | 160054 | 320101 | 101 | 320000 | 100 | 320010 | 300 | 2560206 | 320110 | 200 | 320016 | 200 | 320016 | 1 | 320000 | 100 |
Result (median cycles for code divided by count): 2.0006
| retire uop (01) | cycle (02) | schedule uop (52) | schedule int uop (53) | schedule ldst uop (55) | dispatch int uop (56) | dispatch ldst uop (58) | int uops in schedulers (59) | simd uops in schedulers (5a) | dispatch uop (78) | map int uop (7c) | map ldst uop (7d) | map int uop inputs (7f) | map ldst uop inputs (80) | ? int output thing (e9) | ? ldst retires (ed) | ? int retires (ef) |
| 320025 | 160201 | 320047 | 11 | 320036 | 10 | 320010 | 30 | 1743112 | 320020 | 20 | 320016 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160051 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320058 | 30 | 1659608 | 320068 | 20 | 320072 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320025 | 160108 | 320047 | 11 | 320036 | 10 | 320058 | 30 | 2148426 | 320068 | 20 | 320072 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160043 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320000 | 1 | 320000 | 10 |
| 320024 | 160085 | 320011 | 11 | 320000 | 10 | 320000 | 30 | 2559982 | 320010 | 20 | 320000 | 20 | 320072 | 1 | 320000 | 10 |