Icestorm: LD1 (multiple, 4 regs, 2S) measurements

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	30145	4009	1	4008	4000	12000	4000	4000	4000	1	4000
64005	30226	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29480	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29481	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29478	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29482	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29489	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29479	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29479	4001	1	4000	4000	12000	4000	4000	4000	1	4000
64004	29482	4001	1	4000	4000	12000	4000	4000	4000	1	4000

Count: 8

Code:

  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]
  ld1 { v0.2s, v1.2s, v2.2s, v3.2s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320205	160159	320137	101	0	320036	100	0	320058	300	1030468	320158	200	320072	200	320016	1	320000	100
320204	160057	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100
320204	160056	320107	101	0	320006	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100
320204	160048	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320072	1	320000	100
320204	160048	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100
320204	160048	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100
320204	160048	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100
320204	160054	320101	101	0	320000	100	0	320058	300	2561236	320158	200	320072	200	320016	1	320000	100
320204	160104	320101	101	0	320000	100	0	320010	300	1344190	320110	200	320016	200	320016	1	320000	100
320204	160056	320101	101	0	320000	100	0	320010	300	2560040	320110	200	320016	200	320016	1	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	160650	320041	11	0	320030	10	0	320000	30	1754018	320010	20	320000	20	320072	0	1	320000	0	10
320024	160059	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320058	30	1918542	320068	20	320072	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320025	160110	320047	11	0	320036	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	0	320000	10	0	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10

LD1 (multiple, 4 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations