Icestorm: LD1 (multiple, 4 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 4.000

Integer unit issues: 0.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	29937	4021	1	4020	4000	0	12000	4000	0	4000	4000	1	4000
64004	29417	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29429	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29431	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29424	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29450	4001	1	4000	4000	0	12023	4000	0	4000	4000	1	4000
64004	29542	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29426	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29433	4001	1	4000	4000	0	12000	4000	0	4000	4000	1	4000
64004	29425	4001	1	4000	4004	0	12012	4004	0	4004	4000	1	4000

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]
  ld1 { v0.4s, v1.4s, v2.4s, v3.4s }, [x6]

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320205	160182	320137	101	320036	100	320010	300	1024194	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100
320204	160063	320101	101	320000	100	320010	300	2560830	320110	200	320016	200	320016	0	1	320000	0	100
320204	160287	320101	101	320000	100	320010	300	2560296	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100
320205	160373	320131	101	320030	100	320010	300	2560350	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100
320204	160054	320101	101	320000	100	320010	300	2560206	320110	200	320016	200	320016	0	1	320000	0	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? simd retires (ee)	? int retires (ef)
320025	160182	320047	11	320036	10	320010	30	1600248	320020	20	320016	20	320000	0	1	320000	0	10
320024	160054	320011	11	320000	10	320000	30	2560218	320010	20	320000	20	320000	0	1	320000	0	10
320024	160054	320011	11	320000	10	320058	30	2506342	320068	20	320072	20	320016	0	1	320000	0	10
320025	160408	320041	11	320030	10	320000	30	2560272	320010	20	320000	20	320000	0	1	320000	0	10
320024	160051	320011	11	320000	10	320000	30	2560488	320010	20	320000	20	320000	0	1	320000	0	10
320025	160396	320041	11	320030	10	280746	24	2239684	280754	16	280768	20	320000	0	1	320000	0	10
320024	160054	320011	11	320000	10	320000	30	2560272	320010	20	320000	20	320000	0	1	320000	0	10
320025	160357	320041	11	320030	10	320000	30	2560308	320010	20	320000	20	320000	0	1	320000	0	10
320024	160051	320011	11	320000	10	320000	30	2560164	320010	20	320000	20	320000	0	1	320000	0	10
320024	160051	320011	11	320000	10	320058	30	1919380	320068	20	320072	20	320000	0	1	320000	0	10

LD1 (multiple, 4 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations