Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 1 reg, 1D)

Test 1: uops

Code:

  ld1 { v0.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6100529425200510031002100210003000300020001000200010011000
6100429221200110011000100010003000300020001000200010011000
6100429223200110011000100010003000300020001000200010011000
6100429221200110011000100010003000300020001000200010011000
6100429277200110011000100010003000300020001000200010011000
6100429271200110011000100010003000300020001000200010011000
6100429997200110011000100010003000300020001000200010011000
6100429605200110011000100010003000300120001000200010011000
6100429311200110011000100010003000300020001000200010011000
6100429271200110011000100010003000300020001000200010011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020610020070119501091000810002401631002110003265947576669579423960110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602762002610014500081000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002510015070019500121000610001400421001110000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265951276722379475160010300201000010000600202000010000500011000040010
5002410007470014500111000310000400141000310000265938476715279468260010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600962002610013500081000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010
5002410004270012500111000110000400101000010000265943176719679472460010300201000010000600202000010000500011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  ld1 { v0.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205801191601758014580030801588000316201381359714160109200800102001600208000180000100
80204800331601018010180000801078003716194921359995160179200800502001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204800331601018010180000801078003716206611360060160180200800482001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025802551600928006280030800688000016196571359755160010208000020160000800018000010
80024800331600118001180000800108000016197521359804160010208000020160000800018000010
80024800331600118001180000800108003616200631360056160086208004820160000800018000010
80024800331600118001180000800108000016197521359804160010208000020160000800018000010
80024800331600118001180000800108000016186711359804160010208000020160000800018000010
80024800331600118001180000800108000016197161359804160010208000020160000800018000010
80024800331600118001180000800108000016197521359804160010208000020160000800018000010
80024800331600118001180000800108000016197521359804160010208000020160000800018000010
80024800331600118001180000800108000016197521359804160010208000020160000800018000010
80025800661600458002880017800508000016197521359804160010208000020160000800018000010