Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 1 reg, 2D)

Test 1: uops

Code:

  ld1 { v0.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6100529329200510031002100210013003300320021001200010011000
6100429078200110011000100010003000300020001000200010011000
6100429076200110011000100010003000300020001000200010011000
6100429081200110011000100010003000300020001000200010011000
6100429077200110011000100010003000300020001000200010011000
6100429077200110011000100010003000300020001000200010011000
6100429076200110011000100010003000300020001000200010011000
6100429080200110011000100010003000300020001000200010011000
6100429075200110011000100010003000300020001000200010011000
6100429076200110011000100010003000300020001000200010011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020610017870119501091000810002401631001910003265939276667079421560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602782002610013500091000040100
5020410005470103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100
5020410004770103501011000210000401041000310003265950276676679430560110302091000410003602182000810003500011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002510014870019500121000610001400421001110003266008576739079492960020300291000410003600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002510008170023500181000410001400451001210000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010
5002410004970013500111000210000400101000010000265962076724579478060010300201000010000600202000010000500011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  ld1 { v0.2d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205802581601828015280030801578000316201551359701160109200800102001600168000180000100
80204800331601018010180000801078004116204591360627160188200800482001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204803651601498012580024801478004116204861365235160188200800482001600968002580000100
80204800331601018010180000801078000216201881359812160106200800082001600168000180000100
80204800331601018010180000801078003716206601360060160180200800482001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100
80204807801603918024680145803458019416206771365018160501200802112001603368009780000100
80204802601601978014980048801878007816205461366134160262200800882001600168000180000100
80204800331601018010180000801078000316203641359814160110200800082001600168000180000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025801151600848005480030800688000316196821359765160019208001020160000800018000010
80024800331600118001180000800108000016197811359804160010208000020160000800018000010
80024800331600118001180000800108000016197811359804160010208000020160000800018000010
80025800661600458002880017800508000016196741359805160010208000020160000800018000010
80024800331600118001180000800108000016197551359804160010208000020160000800018000010
80024800331600118001180000800108000016197811359804160010208000020160096800188000010
80024800331600118001180000800108007616199801361416160166208008020160000800018000010
80024803481602038010780096801708000016197811359804160010208000020160000800018000010
80024800331600118001180000800108000016197811359804160010208000020160000800018000010
80024800331600118001180000800108000016197811359804160010208000020160000800018000010