Icestorm: LD1 (multiple, post-index, 1 reg, 4H) measurements

Code:

  ld1 { v0.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29546	2005	1003	1002	1002	1000	3000	3000	2000	1000	2000	1001	1000
61004	29118	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29113	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29147	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29113	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29113	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29116	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29115	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29116	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29118	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0041

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100154	70109	50102	10006	10001	40132	10011	10010	2660130	766927	794464	60156	30237	10012	10013	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50205	100081	70113	50108	10004	10001	40135	10011	10003	2659367	766731	794265	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100042	70102	50101	10001	10000	40104	10003	10003	2659475	766767	794301	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100047	70103	50101	10002	10000	40104	10003	10002	2659258	766672	794196	60108	30208	10003	10003	60218	20008	10003	50001	10000	40100
50204	100040	70102	50101	10001	10000	40104	10003	10003	2659266	766673	794207	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100152	70019	50012	10006	10001	40042	10010	10003	2659533	767210	794752	60020	30029	10004	10003	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50025	100079	70023	50018	10004	10001	40045	10013	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100124	70013	50011	10002	10000	40010	10000	10000	2660268	767453	794984	60010	30020	10000	10000	60096	20026	10013	50008	10000	40010
50024	100047	70013	50011	10002	10000	40010	10000	10000	2659566	767231	794764	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8
  ld1 { v0.4h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80115	160174	80144	80030	80158	80003	1620236	1359749	160109	200	80010	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620330	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80036	1620630	1360056	160176	200	80048	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80104	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620347	1359814	160110	200	80008	200	160016	80001	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80026	80291	160126	80079	80047	80104	80002	1619749	1359810	160016	20	80008	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619722	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80025	80066	160045	80028	80017	80050	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619752	1359804	160010	20	80000	20	160000	80001	80000	10

LD1 (multiple, post-index, 1 reg, 4H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations