Icestorm: LD1 (multiple, post-index, 1 reg, 4S) measurements

Code:

  ld1 { v0.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
61005	29454	2013	1007	1006	1006	1000	3000	3000	2000	1000	2000	1001	1000
61004	29077	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29071	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29072	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29561	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29492	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000
61004	29073	2001	1001	1000	1000	1000	3000	3000	2000	1000	2000	1001	1000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50205	100148	70109	50102	10006	10001	40132	10011	10003	2659509	766736	794279	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100054	70103	50101	10002	10000	40104	10003	10003	2659799	766858	794397	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10013	2659897	766873	794421	60162	30239	10015	10014	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100
50204	100049	70103	50101	10002	10000	40104	10003	10003	2659556	766780	794321	60110	30209	10004	10003	60218	20008	10003	50001	10000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
50025	100154	70019	50012	10006	10001	40042	10011	10003	2659356	767168	794702	60020	30029	10004	10003	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10012	2659799	767314	794846	60070	30059	10014	10015	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010
50024	100040	70012	50011	10001	10000	40010	10000	10000	2659377	767182	794708	60010	30020	10000	10000	60020	20000	10000	50001	10000	40010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80205	80115	160175	80145	80030	80158	80003	1620116	1359701	160109	200	80010	200	160020	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160096	80018	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160016	80001	80000	100
80204	80033	160101	80101	80000	80107	80003	1620351	1359814	160110	200	80008	200	160102	80018	80000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
80025	80119	160085	80055	80030	80068	80000	1619651	1359755	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80344	160203	80107	80096	80170	80000	1619718	1359804	160010	20	80000	20	160096	80018	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80033	160011	80011	80000	80010	80000	1619745	1359804	160010	20	80000	20	160000	80001	80000	10
80024	80132	160059	80035	80024	80050	80228	1620473	1366860	160478	20	80240	20	160400	80121	80000	10

LD1 (multiple, post-index, 1 reg, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->2 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations