Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 1 reg, 4S)

Test 1: uops

Code:

  ld1 { v0.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 1.000

Issues: 2.000

Integer unit issues: 1.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6100529454201310071006100610003000300020001000200010011000
6100429077200110011000100010003000300020001000200010011000
6100429073200110011000100010003000300020001000200010011000
6100429071200110011000100010003000300020001000200010011000
6100429072200110011000100010003000300020001000200010011000
6100429073200110011000100010003000300020001000200010011000
6100429561200110011000100010003000300020001000200010011000
6100429492200110011000100010003000300020001000200010011000
6100429073200110011000100010003000300020001000200010011000
6100429073200110011000100010003000300020001000200010011000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5020510014870109501021000610001401321001110003265950976673679427960110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410005470103501011000210000401041000310003265979976685879439760110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310013265989776687379442160162302391001510014602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100
5020410004970103501011000210000401041000310003265955676678079432160110302091000410003602182000810003500011000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
5002510015470019500121000610001400421001110003265935676716879470260020300291000410003600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010012265979976731479484660070300591001410015600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010
5002410004070012500111000110000400101000010000265937776718279470860010300201000010000600202000010000500011000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  ld1 { v0.4s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80205801151601758014580030801588000316201161359701160109200800102001600208000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600968001880000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001600168000180000100
80204800331601018010180000801078000316203511359814160110200800082001601028001880000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0004

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
80025801191600858005580030800688000016196511359755160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024803441602038010780096801708000016197181359804160010208000020160096800188000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024800331600118001180000800108000016197451359804160010208000020160000800018000010
80024801321600598003580024800508022816204731366860160478208024020160400801218000010