Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 1D)

Test 1: uops

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6200530582300710032004100220003000600030002000300010012000
6200430140300110012000100020003000606330002000300010012000
6200430530300110012000100020003000602630002000300010012000
6200430675300110012000100020003000600030002000300010012000
6200430112300110012000100020003000600030002000300010012000
6200430076300110012000100020003000600030002000300010012000
6200430142300110012000100020003000600030002000300010012000
6200430104300110012000100020003000600030002000300010012000
6200430036300110012000100020003000600030002000300010012000
6200430031300110012000100020003000600030002000300010012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100275801105010210006200024013210012200062659422156758478891370113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602803004210013500092000040100
60204100056801035010110002200004010410003200062659613156785878902470113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100
60204100049801035010110002200004010410003200062659532156780478900070113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60025100294800205001210006200024004210012200062659384156924478967970023300292000810003600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200242659843156957078983670083300592002810013600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60025100075800245001910003200024004610012200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100151801105010210006200024013210012200062659282156758878889770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60205100075801145010910003200024013610011200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062661692156924478967770113302092000810003602183001210003500012000040100
60204100047801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
600251001558002050012100062000240042100122000626595191569324789724700233002920008100036003830012100035000120000040010
600241000478001350011100022000040014100032000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002002426599781569650789881700833005920028100136002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002000026595461569362789735700103002020000100006002030000100005000120000040010
600241000478001350011100022000040010100002002426599781569652789882700833005920028100136002030000100005000120000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  ld1 { v0.1d, v1.1d }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020580151240161801311600308013216001035639952002824011720016001420024002180005160000100
160204800472401058010516000080106160008280394128002824011420016001220024010280030160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024010580031160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16002580186240074800401600348004216001033607672024824002720160014202401118003216000010
160024800502400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010
160024800542400118001116000080010160000280059127999824001020160000202400008000116000010
160024800452400118001116000080010160000280059127999824001020160000202400008000116000010