Icestorm: LD1 (multiple, post-index, 2 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29823	3007	1003	2004	1002	2000	3000	6000	3000	2000	3000	1001	2000
62004	29623	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29653	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29622	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29611	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29615	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29616	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29652	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29622	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29620	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100153	80110	50102	10006	20002	40132	10012	20006	2659433	1567600	788920	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60205	100082	80115	50109	10004	20002	40136	10013	20006	2659282	1567588	788897	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60278	30042	10013	50009	20000	40100
60204	100060	80103	50101	10002	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100042	80102	50101	10001	20000	40104	10003	20006	2659343	1567692	788937	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100145	80020	50012	10006	20002	40042	10012	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60025	100181	80025	50019	10004	20002	40046	10013	20000	2659789	1569524	789813	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60098	30042	10013	50009	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100155	80110	50102	10006	20002	40132	10012	20006	2659383	1567566	788901	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100047	80103	50101	10002	20000	40104	10003	20006	2659478	1567772	788982	70113	30209	20008	10003	60278	30042	10013	50009	20000	40100
60204	100047	80103	50101	10002	20000	40104	10003	20006	2659478	1567772	788982	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100081	80103	50101	10002	20000	40104	10003	20024	2659946	1568034	789116	70173	30239	20028	10013	60218	30012	10003	50001	20000	40100
60205	100080	80115	50109	10004	20002	40136	10013	20006	2659559	1567826	789009	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100047	80103	50101	10002	20000	40104	10003	20006	2659478	1567772	788982	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60205	100080	80115	50109	10004	20002	40136	10013	20006	2659910	1568060	789114	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100047	80103	50101	10002	20000	40104	10003	20024	2660698	1568526	789359	70173	30239	20028	10013	60218	30012	10003	50001	20000	40100
60204	100047	80103	50101	10002	20000	40104	10003	20024	2660158	1568154	789188	70173	30239	20028	10013	60218	30012	10003	50001	20000	40100
60205	100080	80115	50109	10004	20002	40136	10013	20006	2659478	1567772	788982	70113	30209	20008	10003	60276	30039	10013	50009	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100153	80020	50012	10006	20002	40042	10012	20006	2659519	1569324	789724	70023	30029	20008	10003	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60025	100080	80025	50019	10004	20002	40046	10013	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60098	30042	10013	50009	20000	40010
60024	100047	80013	50011	10002	20000	40010	10000	20000	2659546	1569362	789735	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8
  ld1 { v0.2d, v1.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80149	240161	80131	160030	80132	160010	357989	504194	240117	200	160014	200	240021	80005	160000	100
160204	80053	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280397	1283936	240114	200	160012	200	240018	80005	160000	100
160204	80045	240105	80105	160000	80106	160008	280392	1280012	240114	200	160012	200	240018	80005	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80189	240077	80041	160036	80043	160010	320076	880248	240027	20	160014	20	240000	80001	160000	10
160025	80108	240074	80040	160034	80042	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80102	240011	80011	160000	80010	160192	307886	1012978	240306	20	160224	20	240000	80001	160000	10
160024	80062	240011	80011	160000	80010	160000	280051	1280232	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160192	326810	824014	240306	20	160224	20	240420	80131	160000	10
160024	80744	240291	80141	160150	80140	160240	349352	601438	240380	20	160280	20	240420	80131	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10

LD1 (multiple, post-index, 2 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations