Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 2S)

Test 1: uops

Code:

  ld1 { v0.2s, v1.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6200529770300710032004100220003000600030002000300010012000
6200429454300110012000100020003000600030002000300010012000
6200429446300110012000100020003000600030002000300010012000
6200429441300110012000100020003000600030002000300010012000
6200429462300110012000100020003000600030002000300010012000
6200429458300110012000100020003000600030002000300010012000
6200429469300110012000100020003000600030002000300010012000
6200429490300110012000100020003000600030002000300010012000
6200429444300110012000100020003000600030002000300010012000
6200429461300110012000100020003000600030002000300010012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0058

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
602051002738011050102100062000240132100122000626597191567760789012701133020920008100036021830012100035000120000040100
602041000608010350101100022000040104100032000626595321567804789000701133020920008100036021630009100035000120000040100
602041000588010350101100022000040104100032000626597751567948789081701133020920008100036021830012100035000120000040100
602041000588010350101100022000040104100032000626597751567948789081701133020920008100036021830012100035000120000040100
602041000588010350101100022000040104100032000626597751567948789081701133020920008100036021830012100035000120000040100
602041000478010350101100022000040104100032000626594781567772788982701133020920008100036021830012100035000120000040100
602041000478010350101100022000040104100032000626594781567772788982701133020920008100036039830100100335003120000040100
602041000588010350101100022000040104100032000626598021567964789090701133020920008100036021830012100035000120000040100
602041000478010350101100022000040104100032000626595051567788788991701133020920008100036021830012100035000120000040100
602041000588010350101100022000040104100032000626597751567948789081701133020920008100036021830012100035000120000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60025100152800205001210006200024004210012200062659384156924478967970023300292000810003600383001210003500012000040010
60025100075800245001910003200024004610013200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100082800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.2s, v1.2s }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100145801105010210006200024013210012200062659243156754478887270113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100061801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60205100078801145010910003200024013610013200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60025100291800205001210006200024004210012200062659573155942079375970023300292000810003600203000010000500012000040010
60024100049800135001110002200004001010000200182660010156961678986970070300502002010010600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100037800125001110001200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60025100082800255001910004200024004610013200002659816156953878982270010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  ld1 { v0.2s, v1.2s }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020680210240223801571600668015916001035159156819424011720016001420024002180005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160205801052401648013016003480132160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100
160204800532401058010516000080106160008280386128019424011420016001220024001880005160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160025803132400728004216003080043160000280051128016424001020160000202400008000116000010
16002580097240074800401600348004216000033605471998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160025800972400748004016003480042160000280057127998224001020160000202400008000116000010
160024800852400118001116000080010160000280057128018024001020160000202400008000116000010