Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 4H)

Test 1: uops

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6200529565300710032004100220003000600030002000300010012000
6200429393300110012000100020003000600030002000300010012000
6200429427300110012000100020003000600030002000300010012000
6200429351300110012000100020003000600030002000300010012000
6200429370300110012000100020003000600030002000300010012000
6200429399300110012000100020003000600030002000300010012000
6200429416300110012000100020003000600030002000300010012000
6200429434300110012000100020003000600030002000300010012000
6200429344300110012000100020003000600030002000300010012000
6200429401300110012000100020003000600030002000300010012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100153801105010210006200024013210012200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602783004210013500092000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60205100124801145010910003200024013610012200062659424156774678896470113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100
60204100042801025010110001200004010410003200062659343156769278893770113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60026100236800325002010008200044007410022200062659573156935678974270023300292000810003600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600983004210013500092000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002662138157108679054270010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100145801105010210006200024013210012200062659383156755478889570113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602783004210013500092000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200242660158156815278918770173302392002810013602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60026100240800325002010008200044007410021200062659514156924678969270022300292000610003600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  ld1 { v0.4h, v1.4h }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020580157240161801311600308013216001034039768001224011720016001420024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100
160204800452401058010516000080106160008280392128001224011420016001220024001880005160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
160025801822400748004016003480042160000280051128016424001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024804772400118001116000080010160000280059128176424001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202401028003016000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800512400118001116000080010160000280057127998224001020160000202400008000116000010