Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 2 regs, 8B)

Test 1: uops

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6200529548300710032004100220003000600030002000300010012000
6200429322300110012000100020003000600030002000300010012000
6200429316300110012000100020003000600030002000300010012000
6200429299300110012000100020003000600030002000300010012000
6200429290300110012000100020003000600030002000300010012000
6200429287300110012000100020003000600030002000300010012000
6200429303300110012000100020003000600030002000300010012000
6200429294300110012000100020003000600030002000300010012000
6200429286300110012000100020003000600030002000300010012000
6200429289300110012000100020003000600030002000300010012000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0047

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60206100180801225011010008200044016410022200062659429156765678893570113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478157027078898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602783004210013500092000040100
60204100057801035010110002200004010410003200062659505156779078899070113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100
60204100047801035010110002200004010410003200062659478156777278898270113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60025100154800205001210006200024004210011200002659542156928278970970010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200242659843156957078983670083300592002810013600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100075800125001110001200004001010000200002659465156931678970770010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60025100075800245001910003200024004610013200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010
60024100042800125001110001200004001010000200002659411156928278969070010300202000010000600203000010000500012000040010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60205100147801105010210006200024013210012200242659838156787878905170173302392002810013602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60205100073801145010910003200024013610011200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100
60204100040801025010110001200004010410003200062659289156766078891970113302092000810003602183001210003500012000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? int retires (ef)
60025100155800205001210006200024004210012200002659492156917878966770010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60025100082800255001910004200024004610013200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010
60025100082800255001910004200024004610013200002659600156939478975370010300202000010000600203000010000500012000040010
60024100049800135001110002200004001010000200002659600156939478975370010300202000010000600203000010000500012000040010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  ld1 { v0.8b, v1.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16020680213240223801571600668015916001035799950402824011720016001420024002180005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160204800472401058010516000080106160008280394128002824011420016001220024001880005160000100
160205800992401648013016003480132160008280396128114424011420016001220024001880005160000100
160204800472401058010516000080106160008280393128798824011420016001220024001880005160000100
160204800752401058010516000080106160008280394128002824011420016001220024001880005160000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0005

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
16002580194240074800401600348004216001032008288001224002720160014202400188000516000010
160024804952400118001116000080010160000280062128098824001020160000202400008000116000010
16002480043240011800111600008001016005634440763829224009820160068202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
160024800432400118001116000080010160000280057127998224001020160000202400008000116000010
16002480043240011800111600008001016005632880479429224009820160068202400008000116000010