Icestorm: LD1 (multiple, post-index, 2 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 3.000

Integer unit issues: 1.001

Load/store unit issues: 2.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
62005	29771	3007	1003	2004	1002	2000	3000	6000	3000	2000	3000	1001	2000
62004	29386	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29338	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29339	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29338	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29338	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29361	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29359	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29338	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000
62004	29343	3001	1001	2000	1000	2000	3000	6000	3000	2000	3000	1001	2000

Test 2: Latency 1->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100149	80110	50102	10006	20002	40132	10012	20006	2659486	1562008	791493	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2663096	1570180	790139	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100054	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60205	100082	80115	50109	10004	20002	40136	10013	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100151	80020	50012	10006	20002	40042	10012	20000	2659542	1569282	789709	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2660842	1570236	790137	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100044	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60025	100075	80024	50019	10003	20002	40046	10013	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010

Test 3: Latency 2->3 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  fmov x1, d1
  eor x8, x8, x1
  eor x8, x8, x1
  add x6, x6, x8

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0049

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60205	100149	80110	50102	10006	20002	40132	10012	20006	2659421	1567588	788915	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60205	100082	80115	50109	10004	20002	40136	10012	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60205	100138	80115	50109	10004	20002	40136	10013	20006	2659613	1567858	789027	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100
60204	100049	80103	50101	10002	20000	40104	10003	20006	2659532	1567804	789000	70113	30209	20008	10003	60218	30012	10003	50001	20000	40100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 7.0042

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule simd uop (54)	schedule ldst uop (55)	dispatch int uop (56)	dispatch simd uop (57)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	ldst uops in schedulers (5b)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map simd uop (7e)	map int uop inputs (7f)	map ldst uop inputs (80)	map simd uop inputs (81)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
60025	100155	80020	50012	10006	20002	40042	10012	20006	2659433	1569350	789721	70023	30029	20008	10003	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60098	30042	10013	50009	20000	40010
60024	100044	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20024	2662678	1571448	790720	70083	30059	20028	10013	60020	30000	10000	50001	20000	40010
60024	100042	80012	50011	10001	20000	40010	10000	20000	2659411	1569282	789690	70010	30020	20000	10000	60020	30000	10000	50001	20000	40010

Test 4: throughput

Count: 8

Code:

  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8
  ld1 { v0.8h, v1.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160205	80175	240164	80130	160034	80132	160010	357991	504194	240117	200	160014	200	240021	80005	160000	100
160204	80059	240105	80105	160000	80106	160010	357989	501882	240117	200	160014	200	240021	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160205	80108	240164	80130	160034	80132	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100
160204	80056	240105	80105	160000	80106	160008	280386	1280248	240114	200	160012	200	240018	80005	160000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.0007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
160025	80181	240074	80040	160034	80042	160000	336048	720218	240010	20	160000	20	240000	80001	160000	10
160025	80111	240071	80041	160030	80042	160058	286820	1216350	240100	20	160072	20	240102	80030	160000	10
160024	80152	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160058	293201	1150524	240100	20	160072	20	240000	80001	160000	10
160024	80054	240011	80011	160000	80010	160000	280051	1280218	240010	20	160000	20	240000	80001	160000	10

LD1 (multiple, post-index, 2 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: Latency 1->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 3: Latency 2->3 roundtrip

100 unrolls and 100 iterations

1000 unrolls and 10 iterations

Test 4: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations