Icestorm: LD1 (multiple, post-index, 3 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29640	4009	1003	3006	1002	3000	3000	9000	4000	3000	4000	1001	3000
63004	29368	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29342	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29343	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29366	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29344	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29841	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29369	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29367	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29344	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120178	320154	80120	240034	80121	240010	260313	756194	320114	200	240014	200	320018	80004	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320090	80020	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320096	80021	240000	100
240204	120055	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240026	120211	320115	80048	240067	80049	240000	260031	1079982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260030	1920018	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120551	320011	80011	240000	80010	240000	260030	1920592	320010	20	240000	20	320096	80021	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260032	1920432	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320090	80021	240000	10

LD1 (multiple, post-index, 3 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations