Icestorm: LD1 (multiple, post-index, 3 regs, 2D) measurements

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29984	4021	1006	3015	1005	3000	3000	9000	4000	3000	4000	1001	3000
63004	29436	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63005	29437	4005	1002	3003	1001	3000	3000	9000	4000	3000	4000	1001	3000
63004	29663	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29373	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29348	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29378	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29375	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29400	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29541	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000

Count: 8

Code:

  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8
  ld1 { v0.2d, v1.2d, v2.2d }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120170	320150	80120	240030	80121	240010	260313	1452194	320114	200	240014	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240008	260319	1927520	320112	200	240012	200	320319	80072	240000	100
240204	120110	320103	80103	240000	80104	240008	260312	1920194	320112	200	240012	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240008	260312	1920194	320112	200	240012	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240155	260467	1677981	320311	200	240180	200	320615	80140	240000	100
240204	121023	320440	80223	240217	80224	240251	260565	1117728	320441	200	240296	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240008	260312	1920194	320112	200	240012	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240008	260312	1920194	320112	200	240012	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240008	260312	1920194	320112	200	240012	200	320016	80003	240000	100
240204	120053	320103	80103	240000	80104	240056	260367	842264	320177	200	240068	200	320016	80003	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	120195	320064	80030	240034	80031	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240025	120101	320060	80030	240030	80031	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240025	120103	320061	80031	240030	80031	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10
240024	120043	320011	80011	240000	80010	240000	260031	1919982	320010	20	240000	20	320000	80001	240000	10

LD1 (multiple, post-index, 3 regs, 2D)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations