Icestorm: LD1 (multiple, post-index, 3 regs, 2S) measurements

Code:

  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29557	4009	1003	3006	1002	3000	3000	9000	4000	3000	4000	1001	3000
63004	29301	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29345	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29313	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29328	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29316	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29340	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29692	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29513	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29306	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000

Count: 8

Code:

  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8
  ld1 { v0.2s, v1.2s, v2.2s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120152	320150	80120	240030	80121	240010	260313	756194	320114	200	240014	200	320016	80003	240000	100
240204	120054	320110	80104	240006	80104	240010	260314	1452012	320114	200	240014	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320096	80021	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240059	260369	1876575	320181	200	240072	200	320016	80003	240000	100
240204	120045	320103	80103	240000	80104	240008	260313	1920012	320112	200	240012	200	320016	80003	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	120178	320064	80030	240034	80031	240000	260030	1080218	320010	20	240000	20	320000	80001	240000	10
240025	120360	320061	80031	240030	80032	240000	260031	1920398	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10
240024	120054	320011	80011	240000	80010	240000	260030	1920218	320010	20	240000	20	320000	80001	240000	10

LD1 (multiple, post-index, 3 regs, 2S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations