Icestorm: LD1 (multiple, post-index, 3 regs, 4S) measurements

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	29715	4009	1003	3006	1002	3000	3000	9000	4000	3000	4000	1001	3000
63004	29347	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29370	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	30052	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29690	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29385	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29380	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29447	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29356	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29343	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000

Count: 8

Code:

  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8
  ld1 { v0.4s, v1.4s, v2.4s }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120167	320157	80121	240036	80121	240010	260313	756248	320114	200	240014	200	320018	80004	240000	100
240204	120056	320110	80104	240006	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240205	120101	320156	80121	240035	80121	240008	260313	1922192	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240205	120101	320159	80121	240038	80122	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100
240204	120047	320103	80103	240000	80104	240008	260312	1920028	320112	200	240012	200	320016	80003	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	120175	320060	80030	240030	80031	240010	260044	1080020	320024	20	240014	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240060	260101	1413824	320092	20	240071	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240059	260096	1246610	320091	20	240072	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10
240024	120051	320011	80011	240000	80010	240000	260030	1920164	320010	20	240000	20	320000	80001	240000	10

LD1 (multiple, post-index, 3 regs, 4S)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations