Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (multiple, post-index, 3 regs, 8B)

Test 1: uops

Code:

  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map ldst uop (7d)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)
6300529574400910033006100230003000900040003000400010013000
6300429403400110013000100030003000900040003000400010013000
6300429403400110013000100030003000900040003000400010013000
6300429389400110013000100030003000900040003000400010013000
6300429402400110013000100030003000900040003000400010013000
6300529394400110013000100030003000900040003000400010013000
6300429371400110013000100030003000900040003000400010013000
6300429366400110013000100030003000900040003000400010013000
6300429400400110013000100030003000900040003000400010013000
6300429400400110013000100030003000900040003000400010013000

Test 2: throughput

Count: 8

Code:

  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  ld1 { v0.8b, v1.8b, v2.8b }, [x6], x8
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
240205120156320150801202400308012124001026031375619432011420024001420032001880004240000100
2402041200623201108010424000680104240008260312192019432011220024001220032001680003240000100
2402041200533201038010324000080104240008260312192019432011220024001220032001680003240000100
2402041200533201038010324000080104240008260312192019432011220024001220032001680003240000100
2402041200533201038010324000080104240008260312192019432011220024001220032001680003240000100
2402051201073201568012124003580121240008260312192073432011220024001220032001680003240000100
2402041200533201038010324000080104240059260369192080632018120024007220032001880004240000100
2402041200713201108010424000680104240008260312192019432011220024001220032001680003240000100
2402041200533201038010324000080104240008260312192019432011220024001220032001680003240000100
2402041200533201038010324000080104240008260312192019432011220024001220032001680003240000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule ldst uop (55)dispatch int uop (56)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)dispatch uop (78)map int uop (7c)map ldst uop (7d)map int uop inputs (7f)map ldst uop inputs (80)? int output thing (e9)? ldst retires (ed)? int retires (ef)
2400251201743200678003124003680031240010260043137775032002420240014203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200008000124000010
2400251201063200648003024003480031240000260030192016432001020240000203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200008000124000010
2400241200393200118001124000080010240000260030192016432001020240000203200008000124000010
2400241200513200118001124000080010240000260030192016432001020240000203200968002124000010
2400241201083200118001124000080010240000260030192016432001020240000203200008000124000010