Icestorm: LD1 (multiple, post-index, 3 regs, 8H) measurements

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 3.000

Issues: 4.000

Integer unit issues: 1.001

Load/store unit issues: 3.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
63005	30115	4021	1006	3015	1005	3000	3000	9000	4000	3000	4000	1001	3000
63004	29403	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29446	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29444	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29442	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29371	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29443	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29443	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29458	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000
63004	29446	4001	1001	3000	1000	3000	3000	9000	4000	3000	4000	1001	3000

Count: 8

Code:

  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8
  ld1 { v0.8h, v1.8h, v2.8h }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 1.5007

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240205	120150	320150	80120	240030	80121	240010	260313	756248	320114	200	240014	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240056	260368	1240558	320177	200	240068	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240204	120056	320103	80103	240000	80104	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100
240205	120119	320151	80121	240030	80121	240008	260312	1920248	320112	200	240012	200	320016	80003	240000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 1.5006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
240025	120173	320067	80031	240036	80031	240010	260043	1080248	320024	20	240014	20	320000	80001	240000	10
240025	120100	320066	80031	240035	80031	240000	260030	1319998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120175	320011	80011	240000	80010	240000	260031	1920232	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10
240024	120045	320011	80011	240000	80010	240000	260030	1919998	320010	20	240000	20	320000	80001	240000	10

LD1 (multiple, post-index, 3 regs, 8H)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations