Icestorm: LD1 (multiple, post-index, 4 regs, 16B) measurements

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop

Initialization

  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 4.000

Issues: 5.000

Integer unit issues: 1.001

Load/store unit issues: 4.000

SIMD/FP unit issues: 0.000

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map ldst uop (7d)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)
64005	30053	5011	1003	4008	1002	4000	3000	12000	5000	4000	5000	1001	4000
64004	29535	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29466	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29485	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29465	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29465	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29464	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64004	29463	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000
64005	29481	5006	1002	4004	1001	4000	3000	12000	5000	4000	5000	1001	4000
64004	29465	5001	1001	4000	1000	4000	3000	12000	5000	4000	5000	1001	4000

Count: 8

Code:

  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8
  ld1 { v0.16b, v1.16b, v2.16b, v3.16b }, [x6], x8

Initialization

  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320205	160167	400152	80116	320036	80116	320010	240309	1008194	400113	200	320016	200	400020	80003	320000	100
320204	160054	400109	80103	320006	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320205	160098	400152	80116	320036	80116	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400090	80016	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2568826	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100
320204	160047	400103	80103	320000	80103	320010	240309	2560024	400113	200	320016	200	400020	80003	320000	100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0005

Recorded non-zero counters (first 10 of 64 runs)

retire uop (01)	cycle (02)	schedule uop (52)	schedule int uop (53)	schedule ldst uop (55)	dispatch int uop (56)	dispatch ldst uop (58)	int uops in schedulers (59)	simd uops in schedulers (5a)	dispatch uop (78)	map int uop (7c)	map ldst uop (7d)	map int uop inputs (7f)	map ldst uop inputs (80)	? int output thing (e9)	? ldst retires (ed)	? int retires (ef)
320025	160183	400062	80026	320036	80026	320010	240039	2560024	400023	20	320016	20	400020	80003	320000	10
320024	160043	400011	80011	320000	80010	320058	240078	1252286	400084	20	320072	20	400000	80001	320000	10
320024	160051	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10
320024	160043	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400090	80016	320000	10
320024	160055	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10
320025	160107	400056	80026	320030	80026	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10
320024	160043	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10
320024	160043	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10
320024	160043	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400090	80016	320000	10
320024	160043	400011	80011	320000	80010	320000	240030	2559982	400010	20	320000	20	400000	80001	320000	10

LD1 (multiple, post-index, 4 regs, 16B)

Test 1: uops

1000 unrolls and 1 iteration

Test 2: throughput

100 unrolls and 100 iterations

1000 unrolls and 10 iterations