Apple Microarchitecture Research by Dougall Johnson

M1/A14 P-core (Firestorm): Overview | Base Instructions | SIMD and FP Instructions
M1/A14 E-core (Icestorm):  Overview | Base Instructions | SIMD and FP Instructions

LD1 (single, B)

Test 1: uops

Code:

  ld1 { v0.b }[1], [x6]
  nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop ; nop
  mov x0, 1
  mov x1, 2
  mov x8, 0

(no loop instructions)

1000 unrolls and 1 iteration

Retires (minus 60 nops): 2.000

Issues: 2.002

Integer unit issues: 0.001

Load/store unit issues: 1.000

SIMD/FP unit issues: 1.002

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)
62005297442011110081002010021000030007770200001000100010002000110001000
62004293092003110021000010001000030007770200001000100010002000110001000
62004293022003110021000010001000030007770200001000100010002000110001000
62004293052003110021000010001000030007770200001000100010002000110001000
62004293042003110021000010001000030007770200001000100010002000110001000
62004292992003110021000010001000030007770200001000100010002000110001000
62004292992003110021000010001000030007770200001000100010002000110001000
62004293002003110021000010001000030007770200001000100010002000110001000
62004293042003110021000010001000030007770200001000100010002000110001000
62004292992003110021000010001000030007770200001000100010002000110001000

Test 2: Latency 1->2 roundtrip

Chain cycles: 3

Code:

  ld1 { v0.b }[1], [x6]
  fmov x0, d0
  eor x8, x8, x0
  eor x8, x8, x0
  add x6, x6, x8
  mov x0, 1
  mov x1, 2
  mov x8, 0

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0049

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60205120155701144010120012100013013020031100153209318125773425759846017830249100162003360224100043001240001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100
60204120049701054010120004100003010320007100143210945125849525774546017630247100162003360224100043001240001100001000040100
60204120049701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100
60204120053701054010120004100003010320007100043209017125770525758976011430212100042000867896174373012443348131581002644492
60204120442701634013520020100083023720107100043209071125772725759426011430212100042000860224100043001240001100001000040100
60204120052701054010120004100003010320007100043209017125770525758976011430212100042000860224100043001240001100001000040100

1000 unrolls and 10 iterations

Result (median cycles for code, minus 3 chain cycles): 9.0040

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
60025120166700244001120012100013004020031100163209709125954525792296009030071100162003360044100043001240001100001000040010
60024120047700154001120004100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60025120073700224001620005100013004320029100003209195125931425787416001030020100002000060020100003000040001100001000040010
60024120123700134001120002100003001020000100003209114125928125786756001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010
60024120040700134001120002100003001020000100003208844125916525784496001030020100002000060020100003000040001100001000040010

Test 3: throughput

Count: 8

Code:

  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  ld1 { v0.b }[1], [x6]
  mov x7, x6
  mov x8, x6
  mov x9, x6
  mov x10, x6
  mov x11, x6
  mov x12, x6
  mov x13, x6

(fused SUBS/B.cc loop)

100 unrolls and 100 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16020516015416013910180006800321008002680002300240188407979216010220080004800042008000416000818000080000100
16020516008816014310180010800321008003480040300240554407998216017420080044800442008000416000818000080000100
16020416005316010510180002800021008000080040300240653408019016017420080044800442008000416000818000080000100
16020416004516010410180001800021008000080002300240210407979216010220080004800042008000416000818000080000100
16020416004516010410180001800021008000080002300240124407958416010220080004800042008004416008818000080000100
1397501581311395535682647556911655866478280002300240188407979216010220080004800042008000416000818000080000100
16020416004516010410180001800021008000080002300240112407958416010220080004800042008000416000818000080000100
16020416004516010410180001800021008000080002300240188407979216010220080004800042008000416000818000080000100
16020416005316010510180002800021008000080002300240188407979216010220080004800042028004516009028000080000100
16020416005316010510180002800021008000080002300240058407966216010220080004800042008000416000818000080000100

1000 unrolls and 10 iterations

Result (median cycles for code divided by count): 2.0006

retire uop (01)cycle (02)schedule uop (52)schedule int uop (53)schedule simd uop (54)schedule ldst uop (55)dispatch int uop (56)dispatch simd uop (57)dispatch ldst uop (58)int uops in schedulers (59)simd uops in schedulers (5a)ldst uops in schedulers (5b)dispatch uop (78)map int uop (7c)map ldst uop (7d)map simd uop (7e)map int uop inputs (7f)map ldst uop inputs (80)map simd uop inputs (81)? int output thing (e9)? ldst retires (ed)? simd retires (ee)? int retires (ef)
16002516016116004911800068003210800268000230240188407979216001220800048000420800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002516008016005211800098003210800348000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800451600901800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008000030240106407958416001020800008000020800001600001800008000010
16002416004516001211800018000010800008004030240282407998216008420800448004420800001600001800008000010